s3c2410.h

2410下面通过MOTO手台录音程序；自己用的

#define  TCNTO1 (0x51000020) /*Timer count observation 1*/
#define  TCNTB2 (0x51000024) /*Timer count buffer 2*/
#define  TCMPB2 (0x51000028) /*Timer compare buffer 2*/
#define  TCNTO2 (0x5100002c) /*Timer count observation 2*/
#define  TCNTB3 (0x51000030) /*Timer count buffer 3*/
#define  TCMPB3 (0x51000034) /*Timer compare buffer 3*/
#define  TCNTO3 (0x51000038) /*Timer count observation 3*/
#define  TCNTB4 (0x5100003c) /*Timer count buffer 4*/
#define  TCNTO4 (0x51000040) /*Timer count observation 4*/


/* USB DEVICE*/
#define  FUNC_ADDR_REG     (0x52000140) /*Function address*/
#define  PWR_REG           (0x52000144) /*Power management*/
#define  EP_INT_REG        (0x52000148) /*EP Interrupt ending and clear*/
#define  USB_INT_REG       (0x52000158) /*USB Interrupt ending and clear*/
#define  EP_INT_EN_REG     (0x5200015c) /*Interrupt enable*/
#define  USB_INT_EN_REG    (0x5200016c)
#define  FRAME_NUM1_REG    (0x52000170) /*Frame number lower byte*/
#define  FRAME_NUM2_REG    (0x52000174) /*Frame number higher byte*/
#define  INDEX_REG         (0x52000178) /*Register index*/
#define  MAXP_REG          (0x52000180) /*Endpoint max acket*/
#define  EP0_CSR           (0x52000184) /*Endpoint 0 status*/
#define  IN_CSR1_REG       (0x52000184) /*In endpoint control status*/
#define  IN_CSR2_REG       (0x52000188)
#define  OUT_CSR1_REG      (0x52000190) /*Out endpoint control status*/
#define  OUT_CSR2_REG      (0x52000194)
#define  OUT_FIFO_CNT1_REG (0x52000198) /*Endpoint out write count*/
#define  OUT_FIFO_CNT2_REG (0x5200019c)
#define  EP0_FIFO          (0x520001c0) /*Endpoint 0 FIFO*/
#define  EP1_FIFO          (0x520001c4) /*Endpoint 1 FIFO*/
#define  EP2_FIFO          (0x520001c8) /*Endpoint 2 FIFO*/
#define  EP3_FIFO          (0x520001cc) /*Endpoint 3 FIFO*/
#define  EP4_FIFO          (0x520001d0) /*Endpoint 4 FIFO*/
#define  EP1_DMA_CON       (0x52000200) /*EP1 DMA interface control*/
#define  EP1_DMA_UNIT      (0x52000204) /*EP1 DMA Tx unit counter*/
#define  EP1_DMA_FIFO      (0x52000208) /*EP1 DMA Tx FIFO counter*/
#define  EP1_DMA_TTC_L     (0x5200020c) /*EP1 DMA total Tx counter*/
#define  EP1_DMA_TTC_M     (0x52000210)
#define  EP1_DMA_TTC_H     (0x52000214)
#define  EP2_DMA_CON       (0x52000218) /*EP2 DMA interface control*/
#define  EP2_DMA_UNIT      (0x5200021c) /*EP2 DMA Tx unit counter*/
#define  EP2_DMA_FIFO      (0x52000220) /*EP2 DMA Tx FIFO counter*/
#define  EP2_DMA_TTC_L     (0x52000224) /*EP2 DMA total Tx counter*/
#define  EP2_DMA_TTC_M     (0x52000228)
#define  EP2_DMA_TTC_H     (0x5200022c)
#define  EP3_DMA_CON       (0x52000240) /*EP3 DMA interface control*/
#define  EP3_DMA_UNIT      (0x52000244) /*EP3 DMA Tx unit counter*/
#define  EP3_DMA_FIFO      (0x52000248) /*EP3 DMA Tx FIFO counter*/
#define  EP3_DMA_TTC_L     (0x5200024c) /*EP3 DMA total Tx counter*/
#define  EP3_DMA_TTC_M     (0x52000250)
#define  EP3_DMA_TTC_H     (0x52000254)
#define  EP4_DMA_CON       (0x52000258) /*EP4 DMA interface control*/
#define  EP4_DMA_UNIT      (0x5200025c) /*EP4 DMA Tx unit counter*/
#define  EP4_DMA_FIFO      (0x52000260) /*EP4 DMA Tx FIFO counter*/
#define  EP4_DMA_TTC_L     (0x52000264) /*EP4 DMA total Tx counter*/
#define  EP4_DMA_TTC_M     (0x52000268)
#define  EP4_DMA_TTC_H     (0x5200026c)



/* WATCH DOG TIMER*/
#define  WTCON   (0x53000000) /*Watch-dog timer mode*/
#define  WTDAT   (0x53000004) /*Watch-dog timer data*/
#define  WTCNT   (0x53000008) /*Eatch-dog timer count*/


/* IIC*/
#define  IICCON  (0x54000000) /*IIC control*/
#define  IICSTAT (0x54000004) /*IIC status*/
#define  IICADD  (0x54000008) /*IIC address*/
#define  IICDS   (0x5400000c) /*IIC data shift*/


/* IIS*/
#define  IISCON  (0x55000000) /*IIS Control*/
#define  IISMOD  (0x55000004) /*IIS Mode*/
#define  IISPSR  (0x55000008) /*IIS Prescaler*/
#define  IISFCON (0x5500000c) /*IIS FIFO control*/




/* I/O PORT */
#define  GPACON    (0x56000000) /*Port A control*/
#define  GPADAT    (0x56000004) /*Port A data*/
                        
#define  GPBCON    (0x56000010) /*Port B control*/
#define  GPBDAT    (0x56000014) /*Port B data*/
#define  GPBUP     (0x56000018) /*Pull-up control B*/
                        
#define  GPCCON    (0x56000020) /*Port C control*/
#define  GPCDAT    (0x56000024) /*Port C data*/
#define  GPCUP     (0x56000028) /*Pull-up control C*/
                        
#define  GPDCON    (0x56000030) /*Port D control*/
#define  GPDDAT    (0x56000034) /*Port D data*/
#define  GPDUP     (0x56000038) /*Pull-up control D*/
                        
#define  GPECON    (0x56000040) /*Port E control*/
#define  GPEDAT    (0x56000044) /*Port E data*/
#define  GPEUP     (0x56000048) /*Pull-up control E*/
                        
#define  GPFCON    (0x56000050) /*Port F control*/
#define  GPFDAT    (0x56000054) /*Port F data*/
#define  GPFUP     (0x56000058) /*Pull-up control F*/
                        
#define  GPGCON    (0x56000060) /*Port G control*/
#define  GPGDAT    (0x56000064) /*Port G data*/
#define  GPGUP     (0x56000068) /*Pull-up control G*/
                        
#define  GPHCON    (0x56000070) /*Port H control*/
#define  GPHDAT    (0x56000074) /*Port H data*/
#define  GPHUP     (0x56000078) /*Pull-up control H*/
                        
#define  MISCCR    (0x56000080) /*Miscellaneous control*/
#define  DCLKCON   (0x56000084) /*DCLK0/1 control*/
#define  EXTINT0   (0x56000088) /*External interrupt control  egister 0*/
#define  EXTINT1   (0x5600008c) /*External interrupt control  egister 1*/
#define  EXTINT2   (0x56000090) /*External interrupt control  egister 2*/
#define  EINTFLT0  (0x56000094) /*Reserved*/
#define  EINTFLT1  (0x56000098) /*Reserved*/
#define  EINTFLT2  (0x5600009c) /*External interrupt filter control  egister 2*/
#define  EINTFLT3  (0x560000a0) /*External interrupt filter control  egister 3*/
#define  EINTMASK  (0x560000a4) /*External interrupt mask*/
#define  EINTPEND  (0x560000a8) /*External interrupt ending*/
#define  GSTATUS0  (0x560000ac) /*External in status*/
#define  GSTATUS1  (0x560000b0) /*Chip ID(0x32410000)*/
#define  GSTATUS2  (0x560000b4) /*Reset type*/
#define  GSTATUS3  (0x560000b8) /*Saved data0(32-bit) before entering POWER_OFF mode */
#define  GSTATUS4  (0x560000bc) /*Saved data0(32-bit) before entering POWER_OFF mode */


/* RTC*/

#define  RTCCON    (0x57000040) /*RTC control*/
#define  TICNT     (0x57000044) /*Tick time count*/
#define  RTCALM    (0x57000050) /*RTC alarm control*/
#define  ALMSEC    (0x57000054) /*Alarm second*/
#define  ALMMIN    (0x57000058) /*Alarm minute*/
#define  ALMHOUR   (0x5700005c) /*Alarm Hour*/
#define  ALMDATE   (0x57000060) /*Alarm day      <-- May 06, 2002 SOP*/
#define  ALMMON    (0x57000064) /*Alarm month*/
#define  ALMYEAR   (0x57000068) /*Alarm year*/
#define  RTCRST    (0x5700006c) /*RTC  ound  eset*/
#define  BCDSEC    (0x57000070) /*BCD second*/
#define  BCDMIN    (0x57000074) /*BCD minute*/
#define  BCDHOUR   (0x57000078) /*BCD hour*/
#define  BCDDATE   (0x5700007c) /*BCD day        <-- May 06, 2002 SOP*/
#define  BCDDAY    (0x57000080) /*BCD date       <-- May 06, 2002 SOP*/
#define  BCDMON    (0x57000084) /*BCD month*/
#define  BCDYEAR   (0x57000088) /*BCD year*/



/* ADC*/
#define  ADCCON    (0x58000000) /*ADC control*/
#define  ADCTSC    (0x58000004) /*ADC touch screen control*/
#define  ADCDLY    (0x58000008) /*ADC start or Interval Delay*/
#define  ADCDAT0   (0x5800000c) /*ADC conversion data 0*/
#define  ADCDAT1   (0x58000010) /*ADC conversion data 1  */                 
                        
/* SPI          */
#define  SPCON0    (0x59000000) /*SPI0 control*/
#define  SPSTA0    (0x59000004) /*SPI0 status*/
#define  SPPIN0    (0x59000008) /*SPI0 in control*/
#define  SPPRE0    (0x5900000c) /*SPI0 baud  ate rescaler*/
#define  SPTDAT0   (0x59000010) /*SPI0 Tx data*/
#define  SPRDAT0   (0x59000014) /*SPI0 Rx data*/

#define  SPCON1    (0x59000020) /*SPI1 control*/
#define  SPSTA1    (0x59000024) /*SPI1 status*/
#define  SPPIN1    (0x59000028) /*SPI1 in control*/
#define  SPPRE1    (0x5900002c) /*SPI1 baud  ate rescaler*/
#define  SPTDAT1   (0x59000030) /*SPI1 Tx data*/
#define  SPRDAT1   (0x59000034) /*SPI1 Rx data*/


/* SD Interface*/
#define  SDICON     (0x5a000000) /*SDI control*/
#define  SDIPRE     (0x5a000004) /*SDI baud  ate rescaler*/
#define  SDICARG    (0x5a000008) /*SDI command argument*/
#define  SDICCON    (0x5a00000c) /*SDI command control*/
#define  SDICSTA    (0x5a000010) /*SDI command status*/
#define  SDIRSP0    (0x5a000014) /*SDI  esponse 0*/
#define  SDIRSP1    (0x5a000018) /*SDI  esponse 1*/
#define  SDIRSP2    (0x5a00001c) /*SDI  esponse 2*/
#define  SDIRSP3    (0x5a000020) /*SDI  esponse 3*/
#define  SDIDTIMER  (0x5a000024) /*SDI data/busy timer*/
#define  SDIBSIZE   (0x5a000028) /*SDI block size*/
#define  SDIDCON    (0x5a00002c) /*SDI data control*/
#define  SDIDCNT    (0x5a000030) /*SDI data  emain counter*/
#define  SDIDSTA    (0x5a000034) /*SDI data status*/
#define  SDIFSTA    (0x5a000038) /*SDI FIFO status*/
#define  SDIIMSK    (0x5a000040) /*SDI interrupt mask*/
  
             

/* ISR*/
#define ISR_RESET     ((_ISR_STARTADDRESS+0x0))
#define ISR_UNDEF     ((_ISR_STARTADDRESS+0x4))
#define ISR_SWI       ((_ISR_STARTADDRESS+0x8))
#define ISR_PABORT    ((_ISR_STARTADDRESS+0xc))
#define ISR_DABORT    ((_ISR_STARTADDRESS+0x10))
#define ISR_RESERVED  ((_ISR_STARTADDRESS+0x14))
#define ISR_IRQ       ((_ISR_STARTADDRESS+0x18))
#define ISR_FIQ       ((_ISR_STARTADDRESS+0x1c))

#define ISR_EINT0     ((_ISR_STARTADDRESS+0x20))
#define ISR_EINT1     ((_ISR_STARTADDRESS+0x24))
#define ISR_EINT2     ((_ISR_STARTADDRESS+0x28))
#define ISR_EINT3     ((_ISR_STARTADDRESS+0x2c))
#define ISR_EINT4_7   ((_ISR_STARTADDRESS+0x30))
#define ISR_EINT8_23  ((_ISR_STARTADDRESS+0x34))
#define ISR_NOTUSED6  ((_ISR_STARTADDRESS+0x38))
#define ISR_BAT_FLT   ((_ISR_STARTADDRESS+0x3c))
#define ISR_TICK      ((_ISR_STARTADDRESS+0x40))
#define ISR_WDT       ((_ISR_STARTADDRESS+0x44))
#define ISR_TIMER0    ((_ISR_STARTADDRESS+0x48))
#define ISR_TIMER1    ((_ISR_STARTADDRESS+0x4c))
#define ISR_TIMER2    ((_ISR_STARTADDRESS+0x50))
#define ISR_TIMER3    ((_ISR_STARTADDRESS+0x54))
#define ISR_TIMER4    ((_ISR_STARTADDRESS+0x58))
#define ISR_UART2     ((_ISR_STARTADDRESS+0x5c))
#define ISR_LCD       ((_ISR_STARTADDRESS+0x60))
#define ISR_DMA0      ((_ISR_STARTADDRESS+0x64))
#define ISR_DMA1      ((_ISR_STARTADDRESS+0x68))
#define ISR_DMA2      ((_ISR_STARTADDRESS+0x6c))
#define ISR_DMA3      ((_ISR_STARTADDRESS+0x70))
#define ISR_SDI       ((_ISR_STARTADDRESS+0x74))
#define ISR_SPI0      ((_ISR_STARTADDRESS+0x78))
#define ISR_UART1     ((_ISR_STARTADDRESS+0x7c))
#define ISR_NOTUSED24 ((_ISR_STARTADDRESS+0x80))
#define ISR_USBD      ((_ISR_STARTADDRESS+0x84))
#define ISR_USBH      ((_ISR_STARTADDRESS+0x88))
#define ISR_IIC       ((_ISR_STARTADDRESS+0x8c))
#define ISR_UART0     ((_ISR_STARTADDRESS+0x90))
#define ISR_SPI1      ((_ISR_STARTADDRESS+0x94))
#define ISR_RTC       ((_ISR_STARTADDRESS+0x98))
#define ISR_ADC       ((_ISR_STARTADDRESS+0x9c))


/* PENDING BIT*/
#define BIT_EINT0      (0x1)
#define BIT_EINT1      (0x1<<1)
#define BIT_EINT2      (0x1<<2)
#define BIT_EINT3      (0x1<<3)
#define BIT_EINT4_7    (0x1<<4)
#define BIT_EINT8_23   (0x1<<5)
#define BIT_NOTUSED6   (0x1<<6)
#define BIT_BAT_FLT    (0x1<<7)
#define BIT_TICK       (0x1<<8)
#define BIT_WDT        (0x1<<9)
#define BIT_TIMER0     (0x1<<10)
#define BIT_TIMER1     (0x1<<11)
#define BIT_TIMER2     (0x1<<12)
#define BIT_TIMER3     (0x1<<13)
#define BIT_TIMER4     (0x1<<14)
#define BIT_UART2      (0x1<<15)
#define BIT_LCD        (0x1<<16)
#define BIT_DMA0       (0x1<<17)
#define BIT_DMA1       (0x1<<18)
#define BIT_DMA2       (0x1<<19)
#define BIT_DMA3       (0x1<<20)
#define BIT_SDI        (0x1<<21)
#define BIT_SPI0       (0x1<<22)
#define BIT_UART1      (0x1<<23)
#define BIT_NOTUSED24  (0x1<<24)
#define BIT_USBD       (0x1<<25)
#define BIT_USBH       (0x1<<26)
#define BIT_IIC        (0x1<<27)
#define BIT_UART0      (0x1<<28)
#define BIT_SPI1       (0x1<<29)
#define BIT_RTC        (0x1<<30)
#define BIT_ADC        (0x1<<31)
#define BIT_ALLMSK     (0xffffffff)

#define BIT_SUB_ALLMSK (0x7ff)
#define BIT_SUB_ADC    (0x1<<10)
#define BIT_SUB_TC     (0x1<<9)
#define BIT_SUB_ERR2   (0x1<<8)
#define BIT_SUB_TXD2   (0x1<<7)
#define BIT_SUB_RXD2   (0x1<<6)
#define BIT_SUB_ERR1   (0x1<<5)
#define BIT_SUB_TXD1   (0x1<<4)
#define BIT_SUB_RXD1   (0x1<<3)
#define BIT_SUB_ERR0   (0x1<<2)
#define BIT_SUB_TXD0   (0x1<<1)
#define BIT_SUB_RXD0   (0x1<<0)





#ifdef __cplusplus
}
#endif

#endif	/* INCintegratorh */