s3c2410.h

2410下面通过MOTO手台录音程序；自己用的

/* integrator.h - ARM Integrator header file */

/* Copyright 1999-2002 Wind River Systems, Inc. */
/* Copyright 1999-2000 ARM Limited */


#ifndef	INCintegratorh
#define	INCintegratorh

#ifdef __cplusplus
extern "C" {
#endif
#define BSP_VTS
#define TARGET_INTEGRATOR

/* Flash definitions */



/*
 * It is not necessary to define SYS_FLASH_TYPE as FLASH_28F320 as
 * auto-identification correctly identifies the Flash part.
 */



#define INTEGRATOR_SYSCLK   30000000		/* System bus clock */
#define INTEGRATOR_CLK24MHZ 30000000		/* KMI/Timer clock */









#define AMBA_INT_NUM_LEVELS	32

#define AMBA_INT_CSR_MASK	0xFFFFFFFF /* Mask out invalid status bits */


/* Interrupt levels */

#define INT_LVL_ADC             31
#define INT_LVL_RTC             30
#define INT_LVL_SPI_1           29
#define INT_LVL_UART_0  	28	/* UART 0 */
#define INT_LVL_IIC             27
#define INT_LVL_USBH            26
#define INT_LVL_USBD            25
#define INT_LVL_UART_1		23	/* UART 1 */
#define INT_LVL_SPI_0           22
#define INT_LVL_SDI             21
#define INT_LVL_DMA_3           20
#define INT_LVL_DMA_2           19
#define INT_LVL_DMA_1           18
#define INT_LVL_DMA_0           17
#define INT_LVL_LCD             16
#define INT_LVL_UART_2          15
#define INT_LVL_TIMER_0		14	/* timer 4 */
#define INT_LVL_TIMER_1		13	/* timer 3 */
#define INT_LVL_WDT             9
#define INT_LVL_TICK            8
#define INT_LVL_nBATT_FLT       7
#define INT_LVL_EINT_8_23       5
#define INT_LVL_EINT_4_7        4
#define INT_LVL_EINT_3          3
#define INT_LVL_EINT_2          2
#define INT_LVL_EINT_1          1
#define INT_LVL_EINT_0          0

/* interrupt vectors */

#define INT_VEC_ADC             IVEC_TO_INUM(INT_LVL_ADC)
#define INT_VEC_RTC             IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_SPI_1           IVEC_TO_INUM(INT_LVL_SPI_1)
#define INT_VEC_UART_0		IVEC_TO_INUM(INT_LVL_UART_0)
#define INT_VEC_IIC             IVEC_TO_INUM(INT_LVL_IIC)
#define INT_VEC_USBH            IVEC_TO_INUM(INT_LVL_USBH)
#define INT_VEC_USBD            IVEC_TO_INUM(INT_LVL_USBD)
#define INT_VEC_UART_1		IVEC_TO_INUM(INT_LVL_UART_1)
#define INT_VEC_SPI_0           IVEC_TO_INUM(INT_LVL_SPI_0)
#define INT_VEC_SDI             IVEC_TO_INUM(INT_LVL_SDI)
#define INT_VEC_DMA_3           IVEC_TO_INUM(INT_LVL_DMA_3)
#define INT_VEC_DMA_2           IVEC_TO_INUM(INT_LVL_DMA_2)
#define INT_VEC_DMA_1           IVEC_TO_INUM(INT_LVL_DMA_1)
#define INT_VEC_DMA_0           IVEC_TO_INUM(INT_LVL_DMA_0)
#define INT_VEC_LCD             IVEC_TO_INUM(INT_LVL_LCD)
#define INT_VEC_UART_2          IVEC_TO_INUM(INT_LVL_UART_2)
#define INT_VEC_TIMER_0		IVEC_TO_INUM(INT_LVL_TIMER_0)
#define INT_VEC_TIMER_1		IVEC_TO_INUM(INT_LVL_TIMER_1)
#define INT_VEC_WDT             IVEC_TO_INUM(INT_LVL_WDT)
#define INT_VEC_TICK            IVEC_TO_INUM(INT_LVL_TICK)
#define INT_VEC_nBATT_FLT       IVEC_TO_INUM(INT_LVL_nBATT_FLT)
#define INT_VEC_EINT_8_23       IVEC_TO_INUM(INT_LVL_EINT_8_23)
#define INT_VEC_EINT_4_7        IVEC_TO_INUM(INT_LVL_EINT_4_7)
#define INT_VEC_EINT_3          IVEC_TO_INUM(INT_LVL_EINT_3)
#define INT_VEC_EINT_2          IVEC_TO_INUM(INT_LVL_EINT_2)
#define INT_VEC_EINT_1          IVEC_TO_INUM(INT_LVL_EINT_1)
#define INT_VEC_EINT_0          IVEC_TO_INUM(INT_LVL_EINT_0)



/* definitions for the AMBA UART */


#define N_SIO_CHANNELS		2
#define N_UART_CHANNELS		N_SIO_CHANNELS
#define N_AMBA_UART_CHANNELS    N_SIO_CHANNELS

#define UART_0_BASE_ADR		0x50000000	/* UART 0 base address */
#define UART_1_BASE_ADR		0x50004000	/* UART 1 base address */




/* Add corresponding INT_VEC definitions for intConnect calls. */

#define SYS_TIMER_INT_VEC (INT_VEC_TIMER_0)
#define AUX_TIMER_INT_VEC (INT_VEC_TIMER_1)



/* Frequency of counter/timers */

#define SYS_TIMER_CLK	(INTEGRATOR_SYSCLK/30)
#define AUX_TIMER_CLK	(INTEGRATOR_SYSCLK/30)





/*
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value))
 * max frequency = rounddown(clock_rate/(min_counter_value))
 * i.e. SYS_CLK_RATE_MAX = SYS_TIMER_CLK
 *      AUX_CLK_RATE_MAX = AUX_TIMER_CLK
 *
 * However, we must set maxima that are sustainable on a running
 * system determined by experimentation.
 *
 * The 720T values have been determined by experimentation, the others
 * need to be checked.
 */

#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK)/0xffff)

#define SYS_CLK_RATE_MAX  SYS_TIMER_CLK


#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK)/0xffff)

#define AUX_CLK_RATE_MAX AUX_TIMER_CLK







/*
 * Max number of END devices we support - we currently set to three for
 * three PCI slots.
 */

/*#define INTEGRATOR_MAX_END_DEVS 3*/



/*add 2410 support */
#define	FCLK    	202800000	
#define M_MDIV		0xa1	
#define M_PDIV		0x3
#define M_SDIV		0x1
#define FCLKCFG		((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)

#define HDIVN1          0
#define HDIVN           1
#define PDIVN           1
#define DIVCFG          ((HDIVN1<<2)+(HDIVN<<1)+PDIVN)     

#if ( HDIVN1 == 1 )
#define HCLK    FCLK/4
#define PCLK    FCLK/4
#endif

#if( HDIVN == 1 )
#define HCLK    FCLK/2
#else
#define HCLK    FCLK
#endif

#if( PDIVN == 1 )
#define PCLK    HCLK/2
#else
#define PCLK    HCLK
#endif 
 

/* fastbus mode */
/*#define R1_nF           0x0     
#define R1_iA           0x0*/

/* synchronous mode */

/*#define R1_nF           0x40000000     
#define R1_iA           0x0*/


/* asynchronous mode */

#define R1_nF           0x40000000     
#define R1_iA           0x80000000


/* Timer prescaler value */
#define TIMER_PRESCALER   68

/*Timer divider value */
#define TIMER_DIVIDER     2

/*==============================================================================*/
/* File Name : 2410addr.h							*/
/* Function  : S3C2410 Define Address Register					*/
/* Program   : Shin, On Pil (SOP)						*/
/* Date      : May 06, 2002							*/
/* Version   : 0.0								*/
/* History									*/
/*   0.0 : Programming start (February 15,2002) -> SOP				*/
/*         INTERRUPT rPRIORITY 0x4a00000a -> 0x4a00000c       (May 02, 2002 SOP)*/
/*         RTC BCD DAY and DATE Register Name Correction      (May 06, 2002 SOP)*/
/*=============================================================================	*/



#undef __BIG_ENDIAN

/* Memory control */
#define rBWSCON    (*(volatile unsigned *)0x48000000) /*Bus width & wait status*/
#define rBANKCON0  (*(volatile unsigned *)0x48000004) /*Boot ROM control*/
#define rBANKCON1  (*(volatile unsigned *)0x48000008) /*BANK1 control*/
#define rBANKCON2  (*(volatile unsigned *)0x4800000c) /*BANK2 cControl*/
#define rBANKCON3  (*(volatile unsigned *)0x48000010) /*BANK3 control*/
#define rBANKCON4  (*(volatile unsigned *)0x48000014) /*BANK4 control*/
#define rBANKCON5  (*(volatile unsigned *)0x48000018) /*BANK5 control*/
#define rBANKCON6  (*(volatile unsigned *)0x4800001c) /*BANK6 control*/
#define rBANKCON7  (*(volatile unsigned *)0x48000020) /*BANK7 control*/
#define rREFRESH   (*(volatile unsigned *)0x48000024) /*DRAM/SDRAM refresh*/
#define rBANKSIZE  (*(volatile unsigned *)0x48000028) /*Flexible Bank Size*/
#define rMRSRB6    (*(volatile unsigned *)0x4800002c) /*Mode register set for SDRAM*/
#define rMRSRB7    (*(volatile unsigned *)0x48000030) /*Mode register set for SDRAM*/


/* USB Host*/


/* INTERRUPT*/
#define rSRCPND     (*(volatile unsigned *)0x4a000000) /*Interrupt request status*/
#define rINTMOD     (*(volatile unsigned *)0x4a000004) /*Interrupt mode control*/
#define rINTMSK     (*(volatile unsigned *)0x4a000008) /*Interrupt mask control*/
#define rPRIORITY   (*(volatile unsigned *)0x4a00000c) /*IRQ priority control*/
#define rINTPND     (*(volatile unsigned *)0x4a000010) /*Interrupt request status*/
#define rINTOFFSET  (*(volatile unsigned *)0x4a000014) /*Interruot request source offset*/
#define rSUBSRCPND  (*(volatile unsigned *)0x4a000018) /*Sub source pending*/
#define rINTSUBMSK  (*(volatile unsigned *)0x4a00001c) /*Interrupt sub mask*/


/* DMA*/
#define rDISRC0     (*(volatile unsigned *)0x4b000000) /*DMA 0 Initial source*/
#define rDISRCC0    (*(volatile unsigned *)0x4b000004) /*DMA 0 Initial source control*/
#define rDIDST0     (*(volatile unsigned *)0x4b000008) /*DMA 0 Initial Destination*/
#define rDIDSTC0    (*(volatile unsigned *)0x4b00000c) /*DMA 0 Initial Destination control*/
#define rDCON0      (*(volatile unsigned *)0x4b000010) /*DMA 0 Control*/
#define rDSTAT0     (*(volatile unsigned *)0x4b000014) /*DMA 0 Status*/
#define rDCSRC0     (*(volatile unsigned *)0x4b000018) /*DMA 0 Current source*/
#define rDCDST0     (*(volatile unsigned *)0x4b00001c) /*DMA 0 Current destination*/
#define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020) /*DMA 0 Mask trigger*/

#define rDISRC1     (*(volatile unsigned *)0x4b000040) /*DMA 1 Initial source*/
#define rDISRCC1    (*(volatile unsigned *)0x4b000044) /*DMA 1 Initial source control*/
#define rDIDST1     (*(volatile unsigned *)0x4b000048) /*DMA 1 Initial Destination*/
#define rDIDSTC1    (*(volatile unsigned *)0x4b00004c) /*DMA 1 Initial Destination control*/
#define rDCON1      (*(volatile unsigned *)0x4b000050) /*DMA 1 Control*/
#define rDSTAT1     (*(volatile unsigned *)0x4b000054) /*DMA 1 Status*/
#define rDCSRC1     (*(volatile unsigned *)0x4b000058) /*DMA 1 Current source*/
#define rDCDST1     (*(volatile unsigned *)0x4b00005c) /*DMA 1 Current destination*/
#define rDMASKTRIG1 (*(volatile unsigned *)0x4b000060) /*DMA 1 Mask trigger*/

#define rDISRC2     (*(volatile unsigned *)0x4b000080) /*DMA 2 Initial source*/
#define rDISRCC2    (*(volatile unsigned *)0x4b000084) /*DMA 2 Initial source control*/
#define rDIDST2     (*(volatile unsigned *)0x4b000088) /*DMA 2 Initial Destination*/
#define rDIDSTC2    (*(volatile unsigned *)0x4b00008c) /*DMA 2 Initial Destination control*/
#define rDCON2      (*(volatile unsigned *)0x4b000090) /*DMA 2 Control*/
#define rDSTAT2     (*(volatile unsigned *)0x4b000094) /*DMA 2 Status*/
#define rDCSRC2     (*(volatile unsigned *)0x4b000098) /*DMA 2 Current source*/
#define rDCDST2     (*(volatile unsigned *)0x4b00009c) /*DMA 2 Current destination*/
#define rDMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) /*DMA 2 Mask trigger*/