disasm.c

nasm的全套源代码,有些我做了些修改,以方便您更方便更容易调试成功,方便学习做编译器

/* disasm.c   where all the _work_ gets done in the Netwide Disassembler
 *
 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
 * Julian Hall. All rights reserved. The software is
 * redistributable under the licence given in the file "Licence"
 * distributed in the NASM archive.
 *
 * initial version 27/iii/95 by Simon Tatham
 */

#include <stdio.h>
#include <string.h>

#include "nasm.h"
#include "disasm.h"
#include "sync.h"
#include "insns.h"

#include "names.c"

extern struct itemplate **itable[];

/*
 * Flags that go into the `segment' field of `insn' structures
 * during disassembly.
 */
#define SEG_RELATIVE 1
#define SEG_32BIT 2
#define SEG_RMREG 4
#define SEG_DISP8 8
#define SEG_DISP16 16
#define SEG_DISP32 32
#define SEG_NODISP 64
#define SEG_SIGNED 128

static int whichreg(long regflags, int regval)
{
#include "regdis.c"

    if (!(REG_AL & ~regflags))
        return R_AL;
    if (!(REG_AX & ~regflags))
        return R_AX;
    if (!(REG_EAX & ~regflags))
        return R_EAX;
    if (!(REG_DL & ~regflags))
        return R_DL;
    if (!(REG_DX & ~regflags))
        return R_DX;
    if (!(REG_EDX & ~regflags))
        return R_EDX;
    if (!(REG_CL & ~regflags))
        return R_CL;
    if (!(REG_CX & ~regflags))
        return R_CX;
    if (!(REG_ECX & ~regflags))
        return R_ECX;
    if (!(FPU0 & ~regflags))
        return R_ST0;
    if (!(REG_CS & ~regflags))
        return (regval == 1) ? R_CS : 0;
    if (!(REG_DESS & ~regflags))
        return (regval == 0 || regval == 2
                || regval == 3 ? sreg[regval] : 0);
    if (!(REG_FSGS & ~regflags))
        return (regval == 4 || regval == 5 ? sreg[regval] : 0);
    if (!(REG_SEG67 & ~regflags))
        return (regval == 6 || regval == 7 ? sreg[regval] : 0);

    /* All the entries below look up regval in an 8-entry array */
    if (regval < 0 || regval > 7)
        return 0;

    if (!((REGMEM | BITS8) & ~regflags))
        return reg8[regval];
    if (!((REGMEM | BITS16) & ~regflags))
        return reg16[regval];
    if (!((REGMEM | BITS32) & ~regflags))
        return reg32[regval];
    if (!(REG_SREG & ~regflags))
        return sreg[regval];
    if (!(REG_CREG & ~regflags))
        return creg[regval];
    if (!(REG_DREG & ~regflags))
        return dreg[regval];
    if (!(REG_TREG & ~regflags))
        return treg[regval];
    if (!(FPUREG & ~regflags))
        return fpureg[regval];
    if (!(MMXREG & ~regflags))
        return mmxreg[regval];
    if (!(XMMREG & ~regflags))
        return xmmreg[regval];

    return 0;
}

static const char *whichcond(int condval)
{
    static int conds[] = {
        C_O, C_NO, C_C, C_NC, C_Z, C_NZ, C_NA, C_A,
        C_S, C_NS, C_PE, C_PO, C_L, C_NL, C_NG, C_G
    };
    return conditions[conds[condval]];
}

/*
 * Process an effective address (ModRM) specification.
 */
static unsigned char *do_ea(unsigned char *data, int modrm, int asize,
                            int segsize, operand * op)
{
    int mod, rm, scale, index, base;

    mod = (modrm >> 6) & 03;
    rm = modrm & 07;

    if (mod == 3) {             /* pure register version */
        op->basereg = rm;
        op->segment |= SEG_RMREG;
        return data;
    }

    op->addr_size = 0;

    if (asize == 16) {
        /*
         * <mod> specifies the displacement size (none, byte or
         * word), and <rm> specifies the register combination.
         * Exception: mod=0,rm=6 does not specify [BP] as one might
         * expect, but instead specifies [disp16].
         */
        op->indexreg = op->basereg = -1;
        op->scale = 1;          /* always, in 16 bits */
        switch (rm) {
        case 0:
            op->basereg = R_BX;
            op->indexreg = R_SI;
            break;
        case 1:
            op->basereg = R_BX;
            op->indexreg = R_DI;
            break;
        case 2:
            op->basereg = R_BP;
            op->indexreg = R_SI;
            break;
        case 3:
            op->basereg = R_BP;
            op->indexreg = R_DI;
            break;
        case 4:
            op->basereg = R_SI;
            break;
        case 5:
            op->basereg = R_DI;
            break;
        case 6:
            op->basereg = R_BP;
            break;
        case 7:
            op->basereg = R_BX;
            break;
        }
        if (rm == 6 && mod == 0) {      /* special case */
            op->basereg = -1;
            if (segsize != 16)
                op->addr_size = 16;
            mod = 2;            /* fake disp16 */
        }
        switch (mod) {
        case 0:
            op->segment |= SEG_NODISP;
            break;
        case 1:
            op->segment |= SEG_DISP8;
            op->offset = (signed char)*data++;
            break;
        case 2:
            op->segment |= SEG_DISP16;
            op->offset = *data++;
            op->offset |= ((unsigned)*data++) << 8;
            break;
        }
        return data;
    } else {
        /*
         * Once again, <mod> specifies displacement size (this time
         * none, byte or *dword*), while <rm> specifies the base
         * register. Again, [EBP] is missing, replaced by a pure
         * disp32 (this time that's mod=0,rm=*5*). However, rm=4
         * indicates not a single base register, but instead the
         * presence of a SIB byte...
         */
        op->indexreg = -1;
        switch (rm) {
        case 0:
            op->basereg = R_EAX;
            break;
        case 1:
            op->basereg = R_ECX;
            break;
        case 2:
            op->basereg = R_EDX;
            break;
        case 3:
            op->basereg = R_EBX;
            break;
        case 5:
            op->basereg = R_EBP;
            break;
        case 6:
            op->basereg = R_ESI;
            break;
        case 7:
            op->basereg = R_EDI;
            break;
        }
        if (rm == 5 && mod == 0) {
            op->basereg = -1;
            if (segsize != 32)
                op->addr_size = 32;
            mod = 2;            /* fake disp32 */
        }
        if (rm == 4) {          /* process SIB */
            scale = (*data >> 6) & 03;
            index = (*data >> 3) & 07;
            base = *data & 07;
            data++;

            op->scale = 1 << scale;
            switch (index) {
            case 0:
                op->indexreg = R_EAX;
                break;
            case 1:
                op->indexreg = R_ECX;
                break;
            case 2:
                op->indexreg = R_EDX;
                break;
            case 3:
                op->indexreg = R_EBX;
                break;
            case 4:
                op->indexreg = -1;
                break;
            case 5:
                op->indexreg = R_EBP;
                break;
            case 6:
                op->indexreg = R_ESI;
                break;
            case 7:
                op->indexreg = R_EDI;
                break;
            }

            switch (base) {
            case 0:
                op->basereg = R_EAX;
                break;
            case 1:
                op->basereg = R_ECX;
                break;
            case 2:
                op->basereg = R_EDX;
                break;
            case 3:
                op->basereg = R_EBX;
                break;
            case 4:
                op->basereg = R_ESP;
                break;
            case 6:
                op->basereg = R_ESI;
                break;
            case 7:
                op->basereg = R_EDI;
                break;
            case 5:
                if (mod == 0) {
                    mod = 2;
                    op->basereg = -1;
                } else
                    op->basereg = R_EBP;
                break;
            }
        }
        switch (mod) {
        case 0:
            op->segment |= SEG_NODISP;
            break;
        case 1:
            op->segment |= SEG_DISP8;
            op->offset = (signed char)*data++;
            break;
        case 2:
            op->segment |= SEG_DISP32;
            op->offset = *data++;
            op->offset |= ((unsigned)*data++) << 8;
            op->offset |= ((long)*data++) << 16;
            op->offset |= ((long)*data++) << 24;
            break;
        }
        return data;
    }
}

/*
 * Determine whether the instruction template in t corresponds to the data
 * stream in data. Return the number of bytes matched if so.
 */
static int matches(struct itemplate *t, unsigned char *data, int asize,
                   int osize, int segsize, int rep, insn * ins)
{
    unsigned char *r = (unsigned char *)(t->code);
    unsigned char *origdata = data;
    int a_used = FALSE, o_used = FALSE;
    int drep = 0;

    if (rep == 0xF2)
        drep = P_REPNE;
    else if (rep == 0xF3)
        drep = P_REP;

    while (*r) {
        int c = *r++;
        if (c >= 01 && c <= 03) {
            while (c--)
                if (*r++ != *data++)
                    return FALSE;
        }
        if (c == 04) {
            switch (*data++) {
            case 0x07:
                ins->oprs[0].basereg = 0;
                break;
            case 0x17:
                ins->oprs[0].basereg = 2;
                break;
            case 0x1F:
                ins->oprs[0].basereg = 3;
                break;
            default:
                return FALSE;
            }
        }
        if (c == 05) {
            switch (*data++) {
            case 0xA1:
                ins->oprs[0].basereg = 4;
                break;
            case 0xA9:
                ins->oprs[0].basereg = 5;
                break;
            default:
                return FALSE;
            }
        }
        if (c == 06) {
            switch (*data++) {
            case 0x06:
                ins->oprs[0].basereg = 0;
                break;
            case 0x0E:
                ins->oprs[0].basereg = 1;
                break;
            case 0x16:
                ins->oprs[0].basereg = 2;
                break;
            case 0x1E:
                ins->oprs[0].basereg = 3;
                break;
            default:
                return FALSE;
            }
        }
        if (c == 07) {
            switch (*data++) {
            case 0xA0:
                ins->oprs[0].basereg = 4;
                break;
            case 0xA8:
                ins->oprs[0].basereg = 5;
                break;
            default:
                return FALSE;
            }
        }
        if (c >= 010 && c <= 012) {
            int t = *r++, d = *data++;
            if (d < t || d > t + 7)
                return FALSE;
            else {
                ins->oprs[c - 010].basereg = d - t;
                ins->oprs[c - 010].segment |= SEG_RMREG;
            }
        }
        if (c == 017)
            if (*data++)
                return FALSE;
        if (c >= 014 && c <= 016) {
            ins->oprs[c - 014].offset = (signed char)*data++;
            ins->oprs[c - 014].segment |= SEG_SIGNED;
        }
        if (c >= 020 && c <= 022)
            ins->oprs[c - 020].offset = *data++;
        if (c >= 024 && c <= 026)
            ins->oprs[c - 024].offset = *data++;
        if (c >= 030 && c <= 032) {
            ins->oprs[c - 030].offset = *data++;
            ins->oprs[c - 030].offset |= (((unsigned)*data++) << 8);
        }
        if (c >= 034 && c <= 036) {
            ins->oprs[c - 034].offset = *data++;
            ins->oprs[c - 034].offset |= (((unsigned)*data++) << 8);
            if (osize == 32) {
                ins->oprs[c - 034].offset |= (((long)*data++) << 16);
                ins->oprs[c - 034].offset |= (((long)*data++) << 24);
            }
            if (segsize != asize)
                ins->oprs[c - 034].addr_size = asize;
        }
        if (c >= 040 && c <= 042) {
            ins->oprs[c - 040].offset = *data++;
            ins->oprs[c - 040].offset |= (((unsigned)*data++) << 8);
            ins->oprs[c - 040].offset |= (((long)*data++) << 16);
            ins->oprs[c - 040].offset |= (((long)*data++) << 24);
        }
        if (c >= 044 && c <= 046) {
            ins->oprs[c - 044].offset = *data++;
            ins->oprs[c - 044].offset |= (((unsigned)*data++) << 8);
            if (asize == 32) {
                ins->oprs[c - 044].offset |= (((long)*data++) << 16);
                ins->oprs[c - 044].offset |= (((long)*data++) << 24);
            }
            if (segsize != asize)
                ins->oprs[c - 044].addr_size = asize;
        }
        if (c >= 050 && c <= 052) {
            ins->oprs[c - 050].offset = (signed char)*data++;
            ins->oprs[c - 050].segment |= SEG_RELATIVE;
        }
        if (c >= 060 && c <= 062) {
            ins->oprs[c - 060].offset = *data++;
            ins->oprs[c - 060].offset |= (((unsigned)*data++) << 8);
            ins->oprs[c - 060].segment |= SEG_RELATIVE;
            ins->oprs[c - 060].segment &= ~SEG_32BIT;
        }