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spi_boot_example.tar.gz可以为大家在使用 Cirrus logic的ARM9芯片是提供帮助

/*==================================================================
 *
 *  This file is part of a small Nand flash bootloader designed to
 *  be loaded via EP93xx SPI boot.
 *
 *  Copyright Cirrus Logic Corporation, 2007.  All rights reserved
 *
 ==================================================================*/

#include <regs.h>


    .text
    .globl _entry

_entry:
    .word 0x43525553
//switch red led off and green led on (chip select for NAND)
    ldr r1, =PEDR	//port E bits 0,1 control GRLED(0) and RDLED(1)
    ldr r2, [r1]
    and r2, r2, #0xfd	// red LED off, green led on
    str r2, [r1]

    ldr sp, =INTERNAL_SRAM_END

//disable IRQ,FIQ
    mrs    r0, cpsr
    orr    r0, r0, #0xc0
    msr    cpsr, r0

//disable watchdog

    ldr r0, =0xaa55
    ldr r1, =WATCHDOG
    str r0, [r1]

    bl uart_setup

    ldr r0, =PADR
    ldr r1, =0x1c
    str r1, [r0]    // set EGPIO2,3,4 high
    ldr r0, =PADDR  
    str r1, [r0]    //enable output

//an initial stack

    ldr sp, =INTERNAL_SRAM_END
    
    // we're booting
    mov r0, #'B'
    bl asm_putchar
    mov r0, #'O'
    bl asm_putchar
    mov r0, #'O'
    bl asm_putchar
    mov r0, #'T'
    bl asm_putchar
    mov r0, #'\n'
    bl asm_putchar

//void start_C(u32 bootmode)
    mov r0, #0
    b start_C

// devcfg value for 32bit: 0x00210028 sdram_cmd 0x00008800 , for 16bit: 0x0021002c sdram_cmd 0x00004600
// int sdram_setup(int sdram_base, int devcfg_value, int sdram_cmd , int dummy);

    .globl sdram_setup

sdram_setup:    
    //
    // Try a 32-bit wide configuration of SDRAM.
    //
    orr     r2, r0, r2
    mov     r0, r1
    ldr     r3, =0x80060000  @ sdram register base
    str     r0, [r3, #0x0010] @ devcfg register for /SDCS0
//*****************************************************************************
//
// Configure the SDRAM based on the supplied settings.
//
//*****************************************************************************
SdramConfig:
    //
    // Set the Initialize and MRS bits
    //
    ldr     r4, =0x80000003
    str     r4, [r3, #0x0004]

    //
    // Delay for 200us.
    //
    mov     r4, #0x3000
delay1:
    subs    r4, r4, #1
    bne     delay1

    //
    // Clear the MRS bit to issue a precharge all.
    //
    ldr     r4, =0x80000001
    str     r4, [r3, #0x0004]

    //
    // Temporarily set the refresh timer to 0x10.
    // Make it really low so that refresh cycles are generated.
    //
    ldr     r4, =0x10
    str     r4, [r3, #0x0008]

    //
    // Delay for at least 80 SDRAM clock cycles.
    //
    mov     r4, #80
delay2:
    subs    r4, r4, #1
    bne     delay2

    //
    // Set the refresh timer to the fastest required for any device that might
    // be used.
    //
    ldr     r4, =0x0210
    str     r4, [r3, #0x0008]

    //
    // Select mode register update mode.
    //
    ldr     r4, =0x80000002
    str     r4, [r3, #0x0004]

    //
    // Program the mode register on the SDRAM.
    //
    ldr     r4, [r2]

    //
    // Select normal operating mode.
    //
    ldr     r4, =0x80000000
    str     r4, [r3, #0x0004]

    //
    // Return to the caller.
    //
    mov     pc, lr


// void set_sp(u32 stack_pointer)

    .globl set_sp
set_sp:
    mov sp, r0
    mov pc, lr


// void set_pc(u32 address)

    .globl set_pc
set_pc:
    mov pc, r0


    .globl asm_putchar
    
/* void asm_putchar(int c) */
/* uses r0, r1, r2   */

asm_putchar:
	ldr	r1, =0x808c0000
3:
	ldr	r2, [r1, #0x18]
	tst	r2, #32
	bne	3b
	str	r0, [r1, #0]
	mov	pc, lr