maiko_boot.s

LCD的程序 3D效果的LCD 很有参考价值

/*
	Initalization for OCHAYA2 Board

	05/03/10	僉儍僢僔儏偺弶婜壔
	05/03/19	MMU偲D-Cache偺弶婜壔傪捛壛

	2005 KOTO Co.,Ltd.
*/
	.arm
	.text
	.align	4

ROMbase:
	.org 	0x0 
	b	_entry		/* nPOR */
	ldr	pc, =_und	/* undef (USE JTAG-ICE??) */
	ldr	pc, =_swi	/* SWI */
	ldr	pc, =_abt	/* Abort prefetch */
	ldr	pc, =_abt	/* Abort data */
	nop
	ldr	pc, =_irq	/* IRQ */
	ldr	pc, =_irq	/* FIQ僥僗僩梡偵IRQ偲摨偠*/

/*  KMC僨僼僅儖僩偺傑傑 */
	.org	0x40 

_start_a:
	.long	_start
_und_a:
	.long	_und
_swi_a:
	.long	_swi
_abt_a:
	.long	_abt
_irq_a:
	.long	_irq
_fiq_a:
	.long	_fiq

_entry:

_start_b:

	bl	_kmc_asm_init

#	bl	_init_cache_mmu	/*僉儍僢僔儏偲mmu傪弶婜壔*/

/*	bl  _init_cache*/

	ldr	pc,=_start

	.global	_kmc_asm_init

/* kmc_asm_init */

_kmc_asm_init:
	mov	pc,lr
	.ltorg



/* MMU偲cache偺弶婜壔 */
	/* 僐儞僩儘乕儖儗僕僗僞偺愝掕價僢僩 */
	.equ	_I_BIT,			(0x1<<12)
	.equ	_D_BIT,			(0x1<<2)
	.equ	_M_BIT,			(0x1)
	.equ	_DCACHE_RR,		(0x1<<14)
	/* MMU偺僙僋僔儑儞偺愝掕價僢僩 */
	.equ	_MMU_TTBIT,		(0x1<<4)
	.equ	_MMU_ID_SECTION,(0x2)
	.equ	_MMU_B_BIT,		(0x1<< 2)
	.equ	_MMU_C_BIT,		(0x1<< 3)
	.equ	_MMU_DOMAIN,	(0xf<<5)
	.equ	_MMU_AP_FULL_ACCESS,(0x3<<10)
	/* 傾僪儗僗傗僙僋僔儑儞扨埵偺僒僀僘*/
	.equ	_TTB_ROM_SECTION_START,		0x00000000
	.equ	_TTB_RAM_SECTION_START,		0x10000000
	.equ	_TTB_ROM_SECTION_SIZE,		0x8		/* 僙僋僔儑儞(MB扨埵)悢 */
	.equ	_TTB_RAM_SECTION_SIZE,		0x8	/* 僙僋僔儑儞(MB扨埵)悢 */
#	.equ	_TTB_START,					0x11000000	 /* 偳偙偵偡傞偐丠丠 */
	.equ	_TTB_START,			0x10400000	 /* 偳偙偵偡傞偐丠丠 */


#	.global _TTB_START


_init_cache_mmu:

	/* cache 偺柍岠壔*/
	mov r0,  #0
	mcr p15, 0, r0, c7, c7, 0

	/* TLB偺柍岠壔 */
	mcr p15, 0, r0, c8, c7, 0

	/*TTB偺儀乕僗傾僪儗僗傪弶婜壔*/
	ldr	r0,=(_TTB_START)
    mcr     p15, 0, r0, c2, c0, 0

	/*僼儔僢僩側儊儌儕儅僢僾偲偟偰MMU傪弶婜壔*/

	ldr r1, =0xfff 	/*儖乕僾僇僂儞僞傪弶婜壔*/
	mov	r2, #((_MMU_ID_SECTION) | (_MMU_TTBIT))
	orr r2, r2, #((_MMU_DOMAIN) | (_MMU_AP_FULL_ACCESS))

	/*TTB偺撪梕傪僙僋僔儑儞偲偟偰弶婜壔
	  偡傋偰偺僙僋僔儑儞(1MB扨埵)傪弶婜壔(僉儍僢僔儏丄僶僢僼傽側偟) */
_loop:
	orr		r3, r2, r1, lsl#20	/*儖乕僾僇僂儞僞傪僔僼僩偟偰杽傔崬傓*/
	str		r3, [r0, r1, lsl#2]
	subs	r1, r1, #1
	bpl		_loop

	/*ROM偺Cbit偺傒棫偰傞*/
	ldr	r0, =_TTB_START;
	orr	r0,r0, #(_TTB_ROM_SECTION_START >> 18)	/*TTB偺ROM偺僄儞僩儕偺傾僪儗僗惗惉*/

	mov r2, #0
_loop1:
	ldr r3, [r0, r2, lsl#2]
	orr r3, r3, #_MMU_C_BIT
	str r3, [r0, r2, lsl#2]
	add r2, r2, #1
	cmp r2, #(_TTB_ROM_SECTION_SIZE)
	blt _loop1		/*彫偝偄(彫偝偄偐摨偠側傜bls)*/

	/*DRAM偺Cbit偺傒棫偰傞(儔僀僩僗儖乕)*/
	ldr	r0, =_TTB_START;
	orr	r0,r0, #(_TTB_RAM_SECTION_START >> 18)	/*TTB偺RAM偺僄儞僩儕偺傾僪儗僗惗惉*/

	mov r2, #0
_loop2:
	ldr r3, [r0, r2, lsl#2]
#	orr r3, r3, #(_MMU_C_BIT | _MMU_B_BIT)
	orr r3, r3, #(_MMU_C_BIT)
	str r3, [r0, r2, lsl#2]
	add r2, r2, #1
	cmp r2, #(_TTB_RAM_SECTION_SIZE)
	blt _loop2		/*彫偝偄(彫偝偄偐摨偠側傜bls)*/


_init_domain:	    /* 僪儊僀儞傪愝掕 */
    mov     r0,#(0x3<<30)		/* 僪儊僀儞15傪僼儖傾僋僙僗偵 */
    mcr     p15, 0, r0, c3, c0, 0

	/* I,D僉儍僢僔儏偲MMU傪桳岠偵偡傞 */
	mrc		p15,0,r0,c1,c0,0
	ldr		r1,=( _I_BIT | _D_BIT | _DCACHE_RR | _M_BIT )
	orr		r0, r0, r1
	mcr		p15,0,r0,c1,c0,0

	mov pc, lr


_init_cache:
	mrc		p15,0,r0,c1,c0,0
	ldr		r1,=( _I_BIT | _D_BIT | _DCACHE_RR )
	orr		r0, r0, r1
	mcr		p15,0,r0,c1,c0,0

	mov pc, lr



/*儊儌儕弶婜壔*/
_dram_init: