📄 std_maiko_io.h~
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#define REN_TEX_CACHE_MISS_REG (GPU_BASE + REN_TEX_CACHE_MISS_OFF )
#define REN_TRANS_PIX_CTR_REG (GPU_BASE + REN_TRANS_PIX_CTR_OFF )
#define REN_ALPHA_BLEND_CTR_REG (GPU_BASE + REN_ALPHA_BLEND_CTR_OFF)
//DPU registers
//DPU: 2DGrachic registers
#define DPU_INT_REG ( MVOUT_BASE + 0x000 )
#define DPU_INT_MSK_REG ( MVOUT_BASE + 0x004 )
#define DPU_MODE_REG ( MVOUT_BASE + 0x008 )
#define DPU_DISP_SIZE_REG ( MVOUT_BASE + 0x00c )
#define DPU_MAX_3DMEM_FETCH_LEN_REG ( MVOUT_BASE + 0x010 )
#define DPU_MAX_VIDEOMEM_FETCH_LEN_REG ( MVOUT_BASE + 0x014 )
#define DPU_LINE_INT_REG ( MVOUT_BASE + 0x018 )
#define DPU_LINE_STATUS_REG ( MVOUT_BASE + 0x01c )
#define DPU_PIX_INT_REG ( MVOUT_BASE + 0x020 )
#define DPU_PIX_STAT_REG ( MVOUT_BASE + 0x024 )
#define DPU_4BIT_CLUT_CTRL_REG ( MVOUT_BASE + 0x028 )
#define DPU_8BIT_CLUT_CTRL_REG ( MVOUT_BASE + 0x02c )
#define DPU_REG_DB_SWAP_REG ( MVOUT_BASE + 0x030 )
#define DPU_DISP_CTRL_REG ( MVOUT_BASE + 0x100 )
#define DPU_2DSCR_MODE_REG ( MVOUT_BASE + 0x104 )
#define DPU_PROCESS_ROW_H_REG ( MVOUT_BASE + 0x108 )
#define DPU_DEF_COL_REG ( MVOUT_BASE + 0x10c )
#define DPU_SCR1_SCROLL_REG ( MVOUT_BASE + 0x110 )
#define DPU_SCR2_SCROLL_REG ( MVOUT_BASE + 0x114 )
#define DPU_SCR3_SCROLL_REG ( MVOUT_BASE + 0x118 )
#define DPU_SCR4_SCROLL_REG ( MVOUT_BASE + 0x11c )
#define DPU_SCR2_WIN_ORG_REG ( MVOUT_BASE + 0x120 )
#define DPU_SCR2_WIN_END_REG ( MVOUT_BASE + 0x124 )
#define DPU_SCR3_WIN_ORG_REG ( MVOUT_BASE + 0x128 )
#define DPU_SCR3_WIN_END_REG ( MVOUT_BASE + 0x12c )
#define DPU_3D_WIN_ORG_REG ( MVOUT_BASE + 0x130 )
#define DPU_3D_WIN_END_REG ( MVOUT_BASE + 0x134 )
#define DPU_VIDEO_WIN_ORG_REG ( MVOUT_BASE + 0x138 )
#define DPU_VIDEO_WIN_END_REG ( MVOUT_BASE + 0x13c )
#define DPU_SCR1_ADDR_REG ( MVOUT_BASE + 0x140 )
#define DPU_SCR2_ADDR_REG ( MVOUT_BASE + 0x144 )
#define DPU_SCR3_ADDR_REG ( MVOUT_BASE + 0x148 )
#define DPU_SCR4_ADDR_REG ( MVOUT_BASE + 0x14c )
#define DPU_SCR1_CHAR_ADDR_REG ( MVOUT_BASE + 0x150 )
#define DPU_SCR2_CHAR_ADDR_REG ( MVOUT_BASE + 0x154 )
#define DPU_SCR3_CHAR_ADDR_REG ( MVOUT_BASE + 0x158 )
#define DPU_SCR4_CHAR_ADDR_REG ( MVOUT_BASE + 0x15c )
#define DPU_FB_ADDR_REG ( MVOUT_BASE + 0x160 )
#define DPU_VIDEO_ADDR_LUMA_REG ( MVOUT_BASE + 0x164 )
#define DPU_VIDEO_ADDR_CB_REG ( MVOUT_BASE + 0x168 )
#define DPU_VIDEO_ADDR_CR_REG ( MVOUT_BASE + 0x16c )
#define DPU_CLUT0_BASE_REG ( MVOUT_BASE + 0x800 )
#define DPU_CLUT1_BASE_REG ( MVOUT_BASE + 0xa00 )
#define DPU_Y2RGB_TRANS_BASE_REG ( MVOUT_BASE + 0xc00 )
#define DPU_CB2RGB_TRANS_BASE_REG ( MVOUT_BASE + 0xc80 )
#define DPU_CR2RGB_TRANS_BASE_REG ( MVOUT_BASE + 0xd00 )
#define DPU_SCR_SCROLL_REG(n) ( DPU_SCR1_SCROLL_REG + (n*4))
#define DPU_SCR_ADDR_REG(n) ( DPU_SCR1_ADDR_REG + (n*4) )
#define DPU_SCR_CHAR_ADDR_REG(n) ( DPU_SCR1_CHAR_ADDR_REG + (n*4))
#define DPU_CLUT_ENTRY(m, n) ( MVOUT_BASE + 0x800 + (0x200*m) + (n*4) )
//DPU: LCDC registers
#define DPU_LCDC_GRAY_PTRN0_REG ( MVOUT_BASE + 0x1000)
#define DPU_LCDC_GRAY_PTRN1_REG ( MVOUT_BASE + 0x1004)
#define DPU_LCDC_GRAY_PTRN2_REG ( MVOUT_BASE + 0x1008)
#define DPU_LCDC_GRAY_PTRN3_REG ( MVOUT_BASE + 0x100c)
#define DPU_LCDC_GRAY_PTRN4_REG ( MVOUT_BASE + 0x1010)
#define DPU_LCDC_GRAY_PTRN5_REG ( MVOUT_BASE + 0x1014)
#define DPU_LCDC_GRAY_PTRN6_REG ( MVOUT_BASE + 0x1018)
#define DPU_LCDC_GRAY_PTRN7_REG ( MVOUT_BASE + 0x101c)
#define DPU_LCDC_GRAY_PTRN8_REG ( MVOUT_BASE + 0x1020)
#define DPU_LCDC_GRAY_PTRN9_REG ( MVOUT_BASE + 0x1024)
#define DPU_LCDC_GRAY_PTRN10_REG ( MVOUT_BASE + 0x1028)
#define DPU_LCDC_GRAY_PTRN11_REG ( MVOUT_BASE + 0x102c)
#define DPU_LCDC_GRAY_PTRN12_REG ( MVOUT_BASE + 0x1030)
#define DPU_LCDC_GRAY_PTRN13_REG ( MVOUT_BASE + 0x1034)
#define DPU_LCDC_GRAY_PTRN14_REG ( MVOUT_BASE + 0x1038)
#define DPU_LCDC_GRAY_PTRN15_REG ( MVOUT_BASE + 0x103c)
#define DPU_LCDC_CLK_DIV_REG ( MVOUT_BASE + 0x1040)
#define DPU_LCDC_STN_EX_LINES_REG ( MVOUT_BASE + 0x1044)
#define DPU_LCDC_ALT_SIG_TIM_REG ( MVOUT_BASE + 0x1048)
#define DPU_LCDC_SIG_POLARITY_REG ( MVOUT_BASE + 0x104c)
#define DPU_LCDC_HSYNC_TIM1_REG ( MVOUT_BASE + 0x1050)
#define DPU_LCDC_HSYNC_TIM2_REG ( MVOUT_BASE + 0x1054)
#define DPU_LCDC_VSYNC_TIM1_REG ( MVOUT_BASE + 0x1058)
#define DPU_LCDC_VSYNC_TIM2_REG ( MVOUT_BASE + 0x105c)
#define DPU_LCDC_GRAY_PTRN_REG(n) ( DPU_LCDC_GRAY_PTRN0_REG + 4*n )
//DPU: DENC registers
#define DPU_DENC_REG_BASE ( MVOUT_BASE + 0x2000 )
#define DPU_DENC_COL_CONV_TBL_BASE ( MVOUT_BASE + 0x2400 )
#define DPU_DENC_SCL_COF_BASE ( MVOUT_BASE + 0x2600 )
#define DPU_DENC_SCL_FACTOR_REG ( MVOUT_BASE + 0x2800 )
#define DPU_DENC_V_OFST_REG0 ( MVOUT_BASE + 0x2804 )
#define DPU_DENC_COL_CONV_TBL(n) ( DPU_DENC_COL_CONV_TBL_BASE + (4*n) )
#define DPU_DENC_SCL_COF(n) ( DPU_DENC_SCL_COF_BASE + (4*n) )
//SDIO registers
//SPU registers
//USB registers
//MVOUT registers
//DMAC registers
//ZSP DMAC registers
/*-------------------------------------
CDIF
-------------------------------------*/
#define CDIF_REG_OFFSET ( 0xC4000000 )
// CDIF v08 register map
#define CDIF_REG_CMD_LEN ( *(unsigned long*)( CDIF_REG_OFFSET + 0x00 ) ) //RW
#define CDIF_REG_READ_LEN ( *(unsigned long*)( CDIF_REG_OFFSET + 0x04 ) ) //RW
#define CDIF_REG_CMD_DATA ( *(unsigned long*)( CDIF_REG_OFFSET + 0x08 ) ) //RW
#define CDIF_REG_READ_DATA ( *(unsigned long*)( CDIF_REG_OFFSET + 0x10 ) ) //R
#define CDIF_REG_CMD_CTRL ( *(unsigned long*)( CDIF_REG_OFFSET + 0x14 ) ) //RW
#define CDIF_REG_SENS ( *(unsigned long*)( CDIF_REG_OFFSET + 0x18 ) ) //R
#define CDIF_REG_TRANS_SECT ( *(unsigned long*)( CDIF_REG_OFFSET + 0x1C ) ) //RW
#define CDIF_REG_TRANS_SIZE ( *(unsigned long*)( CDIF_REG_OFFSET + 0x20 ) ) //RW
#define CDIF_REG_1ST_MEM_ADRS ( *(unsigned long*)( CDIF_REG_OFFSET + 0x24 ) ) //RW
#define CDIF_REG_ERR_BUFF_ADRS ( *(unsigned long*)( CDIF_REG_OFFSET + 0x3C ) ) //RW
#define CDIF_REG_CD_DATA_CMD ( *(unsigned long*)( CDIF_REG_OFFSET + 0x40 ) ) //RW
#define CDIF_REG_SYNC_TIMEOUT ( *(unsigned long*)( CDIF_REG_OFFSET + 0x44 ) ) //RW
#define CDIF_REG_TRANS_TIMEOUT ( *(unsigned long*)( CDIF_REG_OFFSET + 0x48 ) ) //RW
#define CDIF_REG_SECTOR_ADRS ( *(unsigned long*)( CDIF_REG_OFFSET + 0x4C ) ) //R
#define CDIF_REG_SECTOR_MATCH ( *(unsigned long*)( CDIF_REG_OFFSET + 0x50 ) ) //RW
#define CDIF_REG_SUBQ1 ( *(unsigned long*)( CDIF_REG_OFFSET + 0x54 ) ) //RW
#define CDIF_REG_SUBQ2 ( *(unsigned long*)( CDIF_REG_OFFSET + 0x58 ) ) //RW
#define CDIF_REG_SUBQ3 ( *(unsigned long*)( CDIF_REG_OFFSET + 0x5C ) ) //RW
#define CDIF_REG_FOK_GFS ( *(unsigned long*)( CDIF_REG_OFFSET + 0x60 ) ) //RW
#define CDIF_REG_INTERRUPT ( *(unsigned long*)( CDIF_REG_OFFSET + 0x64 ) ) //RW
#define CDIF_REG_INTERRUPT_MASK ( *(unsigned long*)( CDIF_REG_OFFSET + 0x68 ) ) //RW
#define CDIF_REG_CLOCK_DIVIDER ( *(unsigned long*)( CDIF_REG_OFFSET + 0x6C ) ) //RW
#define CDIF_REG_ERR_BUF_INFO ( *(unsigned long*)( CDIF_REG_OFFSET + 0x70 ) ) //R
#define CDIF_REG_ERR_BUF_CLEAR ( *(unsigned long*)( CDIF_REG_OFFSET + 0x74 ) ) //RW
#define CDIF_REG_SUBQ_READ_CMD ( *(unsigned long*)( CDIF_REG_OFFSET + 0x78 ) ) //RW
#define CDIF_REG_INT_WRITE_CMD ( 1 )
#define CDIF_REG_INT_READ_DATA ( 1 << 1 )
#define CDIF_REG_INT_SYNC ( 1 << 2 )
#define CDIF_REG_INT_TRANS_CMP ( 1 << 4 )
#define CDIF_REG_INT_SECT_MATCH ( 1 << 6 )
#define CDIF_REG_INT_EXT_INT ( 1 << 7 )
#define CDIF_REG_INT_SYNC_TOUT ( 1 << 8 )
#define CDIF_REG_INT_TRANS_TOUT ( 1 << 9 )
#define CDIF_REG_INT_DATA_ERROR ( 1 << 12 )
#define CDIF_REG_INT_FOK_ERROR ( 1 << 14 )
#define CDIF_REG_INT_GFS_ERROR ( 1 << 15 )
//VIC registers
#define VIC_IRQ_STATUS (INTC_BASE + 0x000)
#define VIC_IRQ_RAW_STATUS (INTC_BASE + 0x004)
#define VIC_IRQ_ENABLE (INTC_BASE + 0x008)
#define VIC_IRQ_ENABLE_CLEAR (INTC_BASE + 0x00c)
#define VIC_IRQ_FIQ_SWI (INTC_BASE + 0x010)
#define VIC_IRQ_INDEX (INTC_BASE + 0x020)
#define VIC_IRQ_ISR_VECTOR (INTC_BASE + 0x024)
#define VIC_IRQ_LPR (INTC_BASE + 0x028)
#define VIC_IRQ_CPR (INTC_BASE + 0x02c)
#define VIC_FIQ_STATUS (INTC_BASE + 0x100)
#define VIC_FIQ_RAW_STATUS (INTC_BASE + 0x104)
#define VIC_FIQ_ENABLE (INTC_BASE + 0x108)
#define VIC_FIQ_ENABLE_CLEAR (INTC_BASE + 0x10c)
#define VIC_FIQ_INDEX (INTC_BASE + 0x120)
#define VIC_FIQ_ISR_VECTOR (INTC_BASE + 0x124)
#define VIC_FIQ_LPR (INTC_BASE + 0x128)
#define VIC_FIQ_CPR (INTC_BASE + 0x12c)
#define VIC_POLARITY_SELECT (INTC_BASE + 0x200)
#define VIC_EDGE_SELECT (INTC_BASE + 0x204)
#define VIC_RESYNC_SELECT (INTC_BASE + 0x208)
#define VIC_PRIORITY_TABLE_CH0 (INTC_BASE + 0x300)
#define VIC_PRIORITY_TABLE_CH1 (INTC_BASE + 0x308)
#define VIC_PRIORITY_TABLE_CH2 (INTC_BASE + 0x30c)
#define VIC_PRIORITY_TABLE_CH3 (INTC_BASE + 0x30c)
#define VIC_PRIORITY_TABLE_CH4 (INTC_BASE + 0x310)
#define VIC_PRIORITY_TABLE_CH5 (INTC_BASE + 0x314)
#define VIC_PRIORITY_TABLE_CH6 (INTC_BASE + 0x318)
#define VIC_PRIORITY_TABLE_CH7 (INTC_BASE + 0x31c)
#define VIC_PRIORITY_TABLE_CH8 (INTC_BASE + 0x320)
#define VIC_PRIORITY_TABLE_CH9 (INTC_BASE + 0x324)
#define VIC_PRIORITY_TABLE_CH10 (INTC_BASE + 0x328)
#define VIC_PRIORITY_TABLE_CH11 (INTC_BASE + 0x32c)
#define VIC_PRIORITY_TABLE_CH12 (INTC_BASE + 0x330)
#define VIC_PRIORITY_TABLE_CH13 (INTC_BASE + 0x334)
#define VIC_PRIORITY_TABLE_CH14 (INTC_BASE + 0x338)
#define VIC_PRIORITY_TABLE_CH15 (INTC_BASE + 0x33c)
#define VIC_PRIORITY_TABLE_CH16 (INTC_BASE + 0x340)
#define VIC_PRIORITY_TABLE_CH17 (INTC_BASE + 0x344)
#define VIC_PRIORITY_TABLE_CH18 (INTC_BASE + 0x348)
#define VIC_PRIORITY_TABLE_CH19 (INTC_BASE + 0x34c)
#define VIC_PRIORITY_TABLE_CH20 (INTC_BASE + 0x350)
#define VIC_PRIORITY_TABLE_CH21 (INTC_BASE + 0x354) //(mod: nakajima (050610))
#define VIC_PRIORITY_TABLE_CH22 (INTC_BASE + 0x358)
#define INT_CAUSE_SWI _BIT( 0) // add by tsutaya 2005/5/12
#define INT_PRI_INIT 0x00000007 /* 弶婜抣 */
#define INT_PRI_DEFAULT 0x00000004 /* 揔媂挷惍偺偙偲 */
#define INT_PRI_SWI INT_PRI_INIT
#define INT_PRI_UART1 0x00000002
#define INT_PRI_UART2 0x00000002
#define INT_PRI_WDT INT_PRI_INIT
#define INT_PRI_RTC INT_PRI_INIT
#define INT_PRI_TIMERS12 0x00000003
#define INT_PRI_TIMERS34 0x00000003
#define INT_PRI_GPIO1 INT_PRI_INIT
#define INT_PRI_GPU INT_PRI_INIT
#define INT_PRI_SPU INT_PRI_INIT
#define INT_PRI_SPI INT_PRI_INIT
#define INT_PRI_USB INT_PRI_INIT
#define INT_PRI_DMAC INT_PRI_INIT
#define INT_PRI_SDIO INT_PRI_INIT
#define INT_PRI_CDIF INT_PRI_INIT
#define INT_PRI_PMU INT_PRI_INIT
#define INT_PRI_GPIO_KEYPAD INT_PRI_INIT
#define INT_PRI_ZSP_MAILBOX0 INT_PRI_INIT
#define INT_PRI_ZSP_MAILBOX1 INT_PRI_INIT
#define INT_PRI_ZSP_DMAC INT_PRI_INIT
#define INT_PRI_EXTERNAL_INT INT_PRI_INIT
#define INT_PRI_DPU 0x00000001
#define INT_PRI_GPIO2 INT_PRI_INIT
#endif
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