📄 std_maiko_io.h~
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#define UART1_MSR (UART0_BASE + 0x18)
#define UART1_SCRATCH (UART0_BASE + 0x1c)
#define UART1_DLL (UART0_BASE + 0x00) //accessible when DLAB = 1
#define UART1_DLH (UART0_BASE + 0x04) //accessible when DLAB = 1
#define UART1_SVL (UART0_BASE + 0x20)
#define UART1_SVM (UART0_BASE + 0x24)
#define UART1_SVH (UART0_BASE + 0x28)
#define UART1_SSR (UART0_BASE + 0x2c)
#define UART1_SCR (UART0_BASE + 0x2c)
#define UART2_RBR (UART1_BASE + 0x00) //accessible when DLAB = 0
#define UART2_THR (UART1_BASE + 0x00) //accessible when DLAB = 0
#define UART2_IER (UART1_BASE + 0x04) //accessible when DLAB = 0
#define UART2_IIR (UART1_BASE + 0x08)
#define UART2_FCR (UART1_BASE + 0x08)
#define UART2_LCR (UART1_BASE + 0x0c)
#define UART2_MCR (UART1_BASE + 0x10)
#define UART2_LSR (UART1_BASE + 0x14)
#define UART2_MSR (UART1_BASE + 0x18)
#define UART2_SCRATCH (UART1_BASE + 0x1c)
#define UART2_DLL (UART1_BASE + 0x00) //accessible when DLAB = 1
#define UART2_DLH (UART1_BASE + 0x04) //accessible when DLAB = 1
#define UART2_SVL (UART1_BASE + 0x20)
#define UART2_SVM (UART1_BASE + 0x24)
#define UART2_SVH (UART1_BASE + 0x28)
#define UART2_SSR (UART1_BASE + 0x2c)
#define UART2_SCR (UART1_BASE + 0x2c)
#define UART_OFFSET (UART1_BASE-UART0_BASE)
//1,2嫟梡
#define UART_RBR(n) (UART0_BASE + UART_OFFSET*n + 0x00) //accessible when DLAB = 0
#define UART_THR(n) (UART0_BASE + UART_OFFSET*n + 0x00) //accessible when DLAB = 0
#define UART_IER(n) (UART0_BASE + UART_OFFSET*n + 0x04) //accessible when DLAB = 0
#define UART_IIR(n) (UART0_BASE + UART_OFFSET*n + 0x08)
#define UART_FCR(n) (UART0_BASE + UART_OFFSET*n + 0x08)
#define UART_LCR(n) (UART0_BASE + UART_OFFSET*n + 0x0c)
#define UART_MCR(n) (UART0_BASE + UART_OFFSET*n + 0x10)
#define UART_LSR(n) (UART0_BASE + UART_OFFSET*n + 0x14)
#define UART_MSR(n) (UART0_BASE + UART_OFFSET*n + 0x18)
#define UART_SCRATCH(n) (UART0_BASE + UART_OFFSET*n + 0x1c)
#define UART_DLL(n) (UART0_BASE + UART_OFFSET*n + 0x00) //accessible when DLAB = 1
#define UART_DLH(n) (UART0_BASE + UART_OFFSET*n + 0x04) //accessible when DLAB = 1
#define UART_SVL(n) (UART0_BASE + UART_OFFSET*n + 0x20)
#define UART_SVM(n) (UART0_BASE + UART_OFFSET*n + 0x24)
#define UART_SVH(n) (UART0_BASE + UART_OFFSET*n + 0x28)
#define UART_SSR(n) (UART0_BASE + UART_OFFSET*n + 0x2c)
#define UART_SCR(n) (UART0_BASE + UART_OFFSET*n + 0x2c)
//WDT
//Remap unit
//CSSP config register
#define CCSP_ARBPRI_1_4 (CCSP_CONFIG_BASE + 0x08)
#define CCSP_ARBPRI_5_8 (CCSP_CONFIG_BASE + 0x0c)
#define CCSP_ARBPRI_9_12 (CCSP_CONFIG_BASE + 0x10)
#define CCSP_URG_ARBPRI_1_4 (CCSP_CONFIG_BASE + 0x14)
#define CCSP_URG_ARBPRI_5_8 (CCSP_CONFIG_BASE + 0x18)
#define CCSP_URG_ARBPRI_9_12 (CCSP_CONFIG_BASE + 0x1c)
//RTC registers
#define RTC_COUNTER (RTC_BASE + 0x00)
#define RTC_MATCH (RTC_BASE + 0x04)
#define RTC_LOAD (RTC_BASE + 0x08)
#define RTC_MASK (RTC_BASE + 0x0c)
#define RTC_INTERRUPT (RTC_BASE + 0x10)
#define RTC_OUTSTANDING (RTC_BASE + 0x14)
//Maiko config registers
#define MAIKO_CFG_REG_DEV_ID (MAIKO_CONFIG_BASE + 0x00)
#define MAIKO_CFG_REG_DEV_CFG (MAIKO_CONFIG_BASE + 0x04)
#define MAIKO_CFG_REG_RESET (MAIKO_CONFIG_BASE + 0x08)
#define MAIKO_CFG_REG_STATUS (MAIKO_CONFIG_BASE + 0x0c)
#define MAIKO_CFG_REG_KPAD_CFG (MAIKO_CONFIG_BASE + 0x10)
#define MAIKO_CFG_REG_KPAD_INT (MAIKO_CONFIG_BASE + 0x14)
#define MAIKO_CFG_REG_KPAD_D0 (MAIKO_CONFIG_BASE + 0x18)
#define MAIKO_CFG_REG_KPAD_D1 (MAIKO_CONFIG_BASE + 0x1c)
#define MAIKO_CFG_REG_ZSP_CTRL (MAIKO_CONFIG_BASE + 0x20)
#define MAIKO_CFG_REG_ZSP_AHBBASE (MAIKO_CONFIG_BASE + 0x24)
#define MAIKO_CFG_REG_ZSP_MEM_CFG (MAIKO_CONFIG_BASE + 0x28)
#define MAIKO_CFG_REG_TIMER12_INTSTAT (MAIKO_CONFIG_BASE + 0x2c)
#define MAIKO_CFG_REG_TIMER34_INTSTAT (MAIKO_CONFIG_BASE + 0x30)
#define MAIKO_CFG_REG_TIMERS12_INT_ENABLE (MAIKO_CONFIG_BASE + 0x34)
#define MAIKO_CFG_REG_TIMERS34_INT_ENABLE (MAIKO_CONFIG_BASE + 0x38)
//mail box registers
#define MAIKO_CFG_REG_MBOX_SEMA (MAIKO_CONFIG_BASE + 0x100)
#define MAIKO_CFG_REG_MBOX_Z2CINT (MAIKO_CONFIG_BASE + 0x104)
#define MAIKO_CFG_REG_MBOX_C2ZINT (MAIKO_CONFIG_BASE + 0x108)
#define MAIKO_CFG_REG_MBOX_ZINTST (MAIKO_CONFIG_BASE + 0x10c)
#define MAIKO_CFG_REG_MBOX_CINTST (MAIKO_CONFIG_BASE + 0x110)
#define MAIKO_CFG_REG_MBOX_ZINTEN (MAIKO_CONFIG_BASE + 0x114)
#define MAIKO_CFG_REG_MBOX_CINTEN (MAIKO_CONFIG_BASE + 0x118)
//PMU registers
#define MAIKO_PMU_CLK_CFG (PMU_BASE + 0x00)
#define MAIKO_PMU_CLK_CMD (PMU_BASE + 0x04)
#define MAIKO_PMU_STDBY_CMD (PMU_BASE + 0x08)
#define MAIKO_PMU_DEV_PWROFF (PMU_BASE + 0x0c)
#define MAIKO_PMU_INTEN (PMU_BASE + 0x10)
#define MAIKO_PMU_INTST (PMU_BASE + 0x14)
#define MAIKO_PMU_MOD_CLKCTL (PMU_BASE + 0x18)
#define MAIKO_PMU_PLL_CTL (PMU_BASE + 0x1c)
#define MAIKO_PMU_PLL_STATUS (PMU_BASE + 0x20)
//Serial Flash ROM registers
//#define MAIKO_SFLASH_ (SFLASH_BASE + )
//SPI registers
#define MAIKO_SPI0_CFG (SPI_BASE + 0x00)
#define MAIKO_SPI0_CMD (SPI_BASE + 0x04)
#define MAIKO_SPI1_CFG (SPI_BASE + 0x08)
#define MAIKO_SPI1_CMD (SPI_BASE + 0x0c)
#define MAIKO_SPI_ST (SPI_BASE + 0x10)
#define MAIKO_SPI_INTEN (SPI_BASE + 0x14)
#define MAIKO_SPI_INT (SPI_BASE + 0x18)
#define MAIKO_SPI_DBUF0 (SPI_BASE + 0x1c)
#define MAIKO_SPI_DBUF1 (SPI_BASE + 0x20)
//CAU registers
#define MAIKO_CAU_F32_TO_F16 (CAU_BASE + 0x00)
#define MAIKO_CAU_F16_TO_F32 (CAU_BASE + 0x04)
#define MAIKO_CAU_FX32A_TO_F16 (CAU_BASE + 0x08)
#define MAIKO_CAU_F16_TO_FX32A (CAU_BASE + 0x0C)
#define MAIKO_CAU_FX32B_TO_F16 (CAU_BASE + 0x18)
#define MAIKO_CAU_F16_TO_FX32B (CAU_BASE + 0x1C)
#define MAIKO_CAU_COL1555_TO_ABGR (CAU_BASE + 0x20)
#define MAIKO_CAU_COL4444_TO_ABGR (CAU_BASE + 0x24)
#define MAIKO_CAU_ABGR_TO_COL1555 (CAU_BASE + 0x28)
#define MAIKO_CAU_ABGR_TO_COL4444 (CAU_BASE + 0x2c)
//GPU registers
#define GLE_SS_OFF (0x00)
#define GLE_BUS_STATUS_OFF (0x04)
#define GLE_STATUS_OFF (0x08)
#define GLE_INT_STATUS_OFF (0x0c)
#define GLE_INT_OFF (0x10)
#define GLE_CAUSE_OFF (0x14)
#define GLE_INT_ADDR_OFF (0x18)
#define GLE_MAT_REG_OFF (0x1c)
#define GLE_MODE_REG_OFF (0x20)
#define GLE_DRAW_RESULT_OFF (0x24)
#define GLE_CLP_OFF (0x28)
#define GLE_VRP_OFF (0x2c)
#define GLE_VBP_OFF (0x30)
#define GLE_JRP_OFF (0x34)
#define GLE_JRP_POP_OFF (0x38)
#define GLE_DRP_OFF (0x3c)
#define GLE_DATA_RET_STATUS_OFF (0x40)
#define GLE_DEBUG0_MODE_OFF (0x44)
#define GLE_DEBUG0_COUNT_OFF (0x48)
#define GLE_DEBUG1_MODE_OFF (0x4c)
#define GLE_DEBUG1_COUNT_OFF (0x50)
#define GLE_DEBUG2_MODE_OFF (0x54)
#define GLE_DEBUG2_COUNT_OFF (0x58)
#define GLE_SRP_OFF (0x5c)
#define GPU_REVID_OFF (0x7c)
#define REN_STATUS_OFF (0x80)
#define REN_SETTINGS1_OFF (0x84)
#define REN_SETTINGS2_OFF (0x88)
#define REN_INTR_OFF (0x8c)
#define REN_VRAM1_XY_OFF (0x90)
#define REN_VRAM2_XY_OFF (0x94)
#define REN_SYSMEM_OFS_OFF (0x98)
#define REN_MEM_INT_FLUSH_OFF (0x9c)
#define REN_REG_FILE_ACC_OFF (0xA0)
#define REN_PERF_CTR_OFF (0xa4)
#define REN_STALL_CTR_OFF (0xa8)
#define REN_GRAD_PRIM_CTR_OFF (0xac)
#define REN_PP_STALL_CTR_OFF (0xb0)
#define REN_PP_PIX_CTR_OFF (0xb4)
#define REN_DEPTH_TEST_CTR_OFF (0xb8)
#define REN_TEX_CACHE_ACC_OFF (0xbc)
#define REN_TEX_CACHE_REP_OFF (0xc0)
#define REN_TEX_CACHE_MISS_OFF (0xc4)
#define REN_TRANS_PIX_CTR_OFF (0xc8)
#define REN_ALPHA_BLEND_CTR_OFF (0xcc)
#define GLE_SS_REG (GPU_BASE + GLE_SS_OFF )
#define GLE_BUS_STATUS_REG (GPU_BASE + GLE_BUS_STATUS_OFF )
#define GLE_STATUS_REG (GPU_BASE + GLE_STATUS_OFF )
#define GLE_INT_STATUS_REG (GPU_BASE + GLE_INT_STATUS_OFF )
#define GLE_INT_REG (GPU_BASE + GLE_INT_OFF )
#define GLE_INT_EN_REG (GPU_BASE + GLE_INT_OFF )
#define GLE_CAUSE_REG (GPU_BASE + GLE_CAUSE_OFF )
#define GLE_INT_ADDR_REG (GPU_BASE + GLE_INT_ADDR_OFF )
#define GLE_MAT_REG_REG (GPU_BASE + GLE_MAT_REG_OFF )
#define GLE_MODE_REG_REG (GPU_BASE + GLE_MODE_REG_OFF )
#define GLE_DRAW_RESULT_REG (GPU_BASE + GLE_DRAW_RESULT_OFF )
#define GLE_CLP_REG (GPU_BASE + GLE_CLP_OFF )
#define GLE_VRP_REG (GPU_BASE + GLE_VRP_OFF )
#define GLE_VBP_REG (GPU_BASE + GLE_VBP_OFF )
#define GLE_JRP_REG (GPU_BASE + GLE_JRP_OFF )
#define GLE_JRP_POP_REG (GPU_BASE + GLE_JRP_POP_OFF )
#define GLE_DRP_REG (GPU_BASE + GLE_DRP_OFF )
#define GLE_DATA_RET_STATUS_REG (GPU_BASE + GLE_DATA_RET_STATUS_OFF)
#define GLE_DEBUG0_MODE_REG (GPU_BASE + GLE_DEBUG0_MODE_OFF )
#define GLE_DEBUG0_COUNT_REG (GPU_BASE + GLE_DEBUG0_COUNT_OFF )
#define GLE_DEBUG1_MODE_REG (GPU_BASE + GLE_DEBUG1_MODE_OFF )
#define GLE_DEBUG1_COUNT_REG (GPU_BASE + GLE_DEBUG1_COUNT_OFF )
#define GLE_DEBUG2_MODE_REG (GPU_BASE + GLE_DEBUG2_MODE_OFF )
#define GLE_DEBUG2_COUNT_REG (GPU_BASE + GLE_DEBUG2_COUNT_OFF )
#define GLE_SRP_REG (GPU_BASE + GLE_SRP_OFF )
#define GPU_REVID_REG (GPU_BASE + GPU_REVID_OFF )
#define REN_STATUS_REG (GPU_BASE + REN_STATUS_OFF )
#define REN_SETTINGS1_REG (GPU_BASE + REN_SETTINGS1_OFF )
#define REN_SETTINGS2_REG (GPU_BASE + REN_SETTINGS2_OFF )
#define REN_INTR_REG (GPU_BASE + REN_INTR_OFF )
#define REN_VRAM1_XY_REG (GPU_BASE + REN_VRAM1_XY_OFF )
#define REN_VRAM2_XY_REG (GPU_BASE + REN_VRAM2_XY_OFF )
#define REN_SYSMEM_OFS_REG (GPU_BASE + REN_SYSMEM_OFS_OFF )
#define REN_MEM_INT_FLUSH_REG (GPU_BASE + REN_MEM_INT_FLUSH_OFF )
#define REN_REG_FILE_ACC_REG (GPU_BASE + REN_REG_FILE_ACC_OFF )
#define REN_PERF_CTR_REG (GPU_BASE + REN_PERF_CTR_OFF )
#define REN_STALL_CTR_REG (GPU_BASE + REN_STALL_CTR_OFF )
#define REN_GRAD_PRIM_CTR_REG (GPU_BASE + REN_GRAD_PRIM_CTR_OFF )
#define REN_PP_STALL_CTR_REG (GPU_BASE + REN_PP_STALL_CTR_OFF )
#define REN_PP_PIX_CTR_REG (GPU_BASE + REN_PP_PIX_CTR_OFF )
#define REN_DEPTH_TEST_CTR_REG (GPU_BASE + REN_DEPTH_TEST_CTR_OFF )
#define REN_TEX_CACHE_ACC_REG (GPU_BASE + REN_TEX_CACHE_ACC_OFF )
#define REN_TEX_CACHE_REP_REG (GPU_BASE + REN_TEX_CACHE_REP_OFF )
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