📄 std_maiko_io.h~
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//
// std_maiko_io.h
// 2005/02/16 傾儖僼傽斉婰弎
// KOTO Co.,Ltd 2005
//
// maiko-lite 偺儊儌儕媦傃儗僕僗僞偺掕媊
//
// 050418 CAU娭學偺愝掕峏怴
// 050609 GPIO2娭學偺愝掕捛壛
// 050610 VIC偺掕悢傪廋惓( nakajima )
#ifndef _STD_MAIKO_IO_H_
#define _STD_MAIKO_IO_H_
#include "maiko_def.h"
#include "maiko_mmap.h"
//***************************************
// 妱崬傒梫場傪掕媊
#define INT_CAUSE_UART1 _BIT( 1)
#define INT_CAUSE_UART2 _BIT( 2)
#define INT_CAUSE_WDT _BIT( 3)
#define INT_CAUSE_RTC _BIT( 4)
#define INT_CAUSE_TIMERS12 _BIT( 5)
#define INT_CAUSE_TIMERS34 _BIT( 6)
#define INT_CAUSE_GPIO1 _BIT( 7)
#define INT_CAUSE_GPU _BIT( 8)
#define INT_CAUSE_SPU _BIT( 9)
#define INT_CAUSE_SPI _BIT(10)
#define INT_CAUSE_USB _BIT(11)
#define INT_CAUSE_DMAC _BIT(12)
#define INT_CAUSE_SDIO _BIT(13)
#define INT_CAUSE_CDIF _BIT(14)
#define INT_CAUSE_PMU _BIT(15)
#define INT_CAUSE_GPIO_KEYPAD _BIT(16)
#define INT_CAUSE_ZSP_MAILBOX0 _BIT(17)
#define INT_CAUSE_ZSP_MAILBOX1 _BIT(18)
#define INT_CAUSE_ZSP_DMAC _BIT(19)
#define INT_CAUSE_EXTERNAL_INT _BIT(20)
#define INT_CAUSE_DPU _BIT(21)
#define INT_CAUSE_GPIO2 _BIT(22)
// Memory contorller registers
#define MEMC_CONFIG_REG (MEMC_REG_BASE + 0x00)
#define MEMC_REFINT_REG (MEMC_REG_BASE + 0x04)
#define MEMC_REFCTL_REG (MEMC_REG_BASE + 0x08)
#define MEMC_DDC_REG (MEMC_REG_BASE + 0x0c)
#define MEMC_SRAM1_TIMING_REG (MEMC_REG_BASE + 0x10)
#define MEMC_SRAM2_TIMING_REG (MEMC_REG_BASE + 0x14)
// GPIO registers
// GPIO offset
// add: by nakajima (050609)
#define GPIO1_STATUS_OFST (0x00)
#define GPIO1_RAW_STATUS_OFST (0x04)
#define GPIO1_ENABLE_OFST (0x08)
#define GPIO1_ENABLE_CLEAR_OFST (0x0c)
#define GPIO1_DIRECTION_OFST (0x10)
#define GPIO1_DATA_OUT_OFST (0x14)
#define GPIO1_DATA_IN_OFST (0x18)
#define GPIO1_POLARITY_OFST (0x1c)
#define GPIO1_EDGE_OFST (0x20)
#define GPIO1_RSYNC_OFST (0x24)
#define GPIO2_STATUS_OFST (0x40)
#define GPIO2_RAW_STATUS_OFST (0x44)
#define GPIO2_ENABLE_OFST (0x48)
#define GPIO2_ENABLE_CLEAR_OFST (0x4c)
#define GPIO2_DIRECTION_OFST (0x50)
#define GPIO2_DATA_OUT_OFST (0x54)
#define GPIO2_DATA_IN_OFST (0x58)
#define GPIO2_POLARITY_OFST (0x5c)
#define GPIO2_EDGE_OFST (0x60)
#define GPIO2_RSYNC_OFST (0x64)
#define GPIO3_STATUS_OFST (0x80)
#define GPIO3_RAW_STATUS_OFST (0x84)
#define GPIO3_ENABLE_OFST (0x88)
#define GPIO3_ENABLE_CLEAR_OFST (0x8c)
#define GPIO3_DIRECTION_OFST (0x90)
#define GPIO3_DATA_OUT_OFST (0x94)
#define GPIO3_DATA_IN_OFST (0x98)
#define GPIO3_POLARITY_OFST (0x9c)
#define GPIO3_EDGE_OFST (0xa0)
#define GPIO3_RSYNC_OFST (0xa4)
#define GPIO4_STATUS_OFST (0xc0)
#define GPIO4_RAW_STATUS_OFST (0xc4)
#define GPIO4_ENABLE_OFST (0xc8)
#define GPIO4_ENABLE_CLEAR_OFST (0xcc)
#define GPIO4_DIRECTION_OFST (0xd0)
#define GPIO4_DATA_OUT_OFST (0xd4)
#define GPIO4_DATA_IN_OFST (0xd8)
#define GPIO4_POLARITY_OFST (0xdc)
#define GPIO4_EDGE_OFST (0xe0)
#define GPIO4_RSYNC_OFST (0xe4)
/*
//comment out : by nakajima (050609)
// GPIO 1 registers
#define GPIO11_STATUS (GPIO_BASE + 0x00)
#define GPIO11_RAW_STATUS (GPIO_BASE + 0x04)
#define GPIO11_ENABLE (GPIO_BASE + 0x08)
#define GPIO11_ENABLE_CLEAR (GPIO_BASE + 0x0c)
#define GPIO11_DIRECTION (GPIO_BASE + 0x10)
#define GPIO11_DATA_OUT (GPIO_BASE + 0x14)
#define GPIO11_DATA_IN (GPIO_BASE + 0x18)
#define GPIO11_POLARITY (GPIO_BASE + 0x1c)
#define GPIO11_EDGE (GPIO_BASE + 0x20)
#define GPIO11_RSYNC (GPIO_BASE + 0x24)
#define GPIO12_STATUS (GPIO_BASE + 0x40)
#define GPIO12_RAW_STATUS (GPIO_BASE + 0x44)
#define GPIO12_ENABLE (GPIO_BASE + 0x48)
#define GPIO12_ENABLE_CLEAR (GPIO_BASE + 0x4c)
#define GPIO12_DIRECTION (GPIO_BASE + 0x50)
#define GPIO12_DATA_OUT (GPIO_BASE + 0x54)
#define GPIO12_DATA_IN (GPIO_BASE + 0x58)
#define GPIO12_POLARITY (GPIO_BASE + 0x5c)
#define GPIO12_EDGE (GPIO_BASE + 0x60)
#define GPIO12_RSYNC (GPIO_BASE + 0x64)
#define GPIO13_STATUS (GPIO_BASE + 0x80)
#define GPIO13_RAW_STATUS (GPIO_BASE + 0x84)
#define GPIO13_ENABLE (GPIO_BASE + 0x88)
#define GPIO13_ENABLE_CLEAR (GPIO_BASE + 0x8c)
#define GPIO13_DIRECTION (GPIO_BASE + 0x90)
#define GPIO13_DATA_OUT (GPIO_BASE + 0x94)
#define GPIO13_DATA_IN (GPIO_BASE + 0x98)
#define GPIO13_POLARITY (GPIO_BASE + 0x9c)
#define GPIO13_EDGE (GPIO_BASE + 0xa0)
#define GPIO13_RSYNC (GPIO_BASE + 0xa4)
#define GPIO14_STATUS (GPIO_BASE + 0xc0)
#define GPIO14_RAW_STATUS (GPIO_BASE + 0xc4)
#define GPIO14_ENABLE (GPIO_BASE + 0xc8)
#define GPIO14_ENABLE_CLEAR (GPIO_BASE + 0xcc)
#define GPIO14_DIRECTION (GPIO_BASE + 0xd0)
#define GPIO14_DATA_OUT (GPIO_BASE + 0xd4)
#define GPIO14_DATA_IN (GPIO_BASE + 0xd8)
#define GPIO14_POLARITY (GPIO_BASE + 0xdc)
#define GPIO14_EDGE (GPIO_BASE + 0xe0)
#define GPIO14_RSYNC (GPIO_BASE + 0xe4)
// GPIO 2 registers
// add: by nakajima (050609)
#define GPIO21_STATUS (GPIO2_BASE + 0x00)
#define GPIO21_RAW_STATUS (GPIO2_BASE + 0x04)
#define GPIO21_ENABLE (GPIO2_BASE + 0x08)
#define GPIO21_ENABLE_CLEAR (GPIO2_BASE + 0x0c)
#define GPIO21_DIRECTION (GPIO2_BASE + 0x10)
#define GPIO21_DATA_OUT (GPIO2_BASE + 0x14)
#define GPIO21_DATA_IN (GPIO2_BASE + 0x18)
#define GPIO21_POLARITY (GPIO2_BASE + 0x1c)
#define GPIO21_EDGE (GPIO2_BASE + 0x20)
#define GPIO21_RSYNC (GPIO2_BASE + 0x24)
#define GPIO22_STATUS (GPIO2_BASE + 0x40)
#define GPIO22_RAW_STATUS (GPIO2_BASE + 0x44)
#define GPIO22_ENABLE (GPIO2_BASE + 0x48)
#define GPIO22_ENABLE_CLEAR (GPIO2_BASE + 0x4c)
#define GPIO22_DIRECTION (GPIO2_BASE + 0x50)
#define GPIO22_DATA_OUT (GPIO2_BASE + 0x54)
#define GPIO22_DATA_IN (GPIO2_BASE + 0x58)
#define GPIO22_POLARITY (GPIO2_BASE + 0x5c)
#define GPIO22_EDGE (GPIO2_BASE + 0x60)
#define GPIO22_RSYNC (GPIO2_BASE + 0x64)
#define GPIO23_STATUS (GPIO2_BASE + 0x80)
#define GPIO23_RAW_STATUS (GPIO2_BASE + 0x84)
#define GPIO23_ENABLE (GPIO2_BASE + 0x88)
#define GPIO23_ENABLE_CLEAR (GPIO2_BASE + 0x8c)
#define GPIO23_DIRECTION (GPIO2_BASE + 0x90)
#define GPIO23_DATA_OUT (GPIO2_BASE + 0x94)
#define GPIO23_DATA_IN (GPIO2_BASE + 0x98)
#define GPIO23_POLARITY (GPIO2_BASE + 0x9c)
#define GPIO23_EDGE (GPIO2_BASE + 0xa0)
#define GPIO23_RSYNC (GPIO2_BASE + 0xa4)
#define GPIO24_STATUS (GPIO2_BASE + 0xc0)
#define GPIO24_RAW_STATUS (GPIO2_BASE + 0xc4)
#define GPIO24_ENABLE (GPIO2_BASE + 0xc8)
#define GPIO24_ENABLE_CLEAR (GPIO2_BASE + 0xcc)
#define GPIO24_DIRECTION (GPIO2_BASE + 0xd0)
#define GPIO24_DATA_OUT (GPIO2_BASE + 0xd4)
#define GPIO24_DATA_IN (GPIO2_BASE + 0xd8)
#define GPIO24_POLARITY (GPIO2_BASE + 0xdc)
#define GPIO24_EDGE (GPIO2_BASE + 0xe0)
#define GPIO24_RSYNC (GPIO2_BASE + 0xe4)
*/
//Timer(1&2) registers
#define TIMERS12_TIMER1 (TIMERS12_BASE + 0x00)
#define TIMERS12_TIMER_PRESCALER1 (TIMERS12_BASE + 0x04)
#define TIMERS12_TIMER_CONTROL1 (TIMERS12_BASE + 0x08)
#define TIMERS12_TIMER2 (TIMERS12_BASE + 0x0c)
#define TIMERS12_TIMER_PRESCALER2 (TIMERS12_BASE + 0x10)
#define TIMERS12_TIMER_CONTROL2 (TIMERS12_BASE + 0x14)
#define TIMERS12_TIMER_TRIGGER_POINT1 (TIMERS12_BASE + 0x18)
#define TIMERS12_TIMER_TRIGGER_POINT2 (TIMERS12_BASE + 0x1c)
#define TIMERS12_TIMER_TRIGGER_POINT3 (TIMERS12_BASE + 0x20)
#define TIMERS12_TIMER_TRIGGER_POINT4 (TIMERS12_BASE + 0x24)
#define TIMERS12_TIMER_TRIGGER_POINT5 (TIMERS12_BASE + 0x28)
#define TIMERS12_TIMER_TRIGGER_POINT6 (TIMERS12_BASE + 0x2c)
#define TIMERS12_TIMER_TRIGGER_POINT(n) (TIMERS12_BASE + 0x18 + (n*4) )
#define TIMERS12_TIMER_TRIGGER_CONTROL (TIMERS12_BASE + 0x30)
//Timer(3&4) registers
#define TIMERS34_TIMER3 (TIMERS34_BASE + 0x00)
#define TIMERS34_TIMER_PRESCALER3 (TIMERS34_BASE + 0x04)
#define TIMERS34_TIMER_CONTROL3 (TIMERS34_BASE + 0x08)
#define TIMERS34_TIMER4 (TIMERS34_BASE + 0x0c)
#define TIMERS34_TIMER_PRESCALER4 (TIMERS34_BASE + 0x10)
#define TIMERS34_TIMER_CONTROL4 (TIMERS34_BASE + 0x14)
#define TIMERS34_TIMER_TRIGGER_POINT1 (TIMERS34_BASE + 0x18)
#define TIMERS34_TIMER_TRIGGER_POINT2 (TIMERS34_BASE + 0x1c)
#define TIMERS34_TIMER_TRIGGER_POINT3 (TIMERS34_BASE + 0x20)
#define TIMERS34_TIMER_TRIGGER_POINT4 (TIMERS34_BASE + 0x24)
#define TIMERS34_TIMER_TRIGGER_POINT5 (TIMERS34_BASE + 0x28)
#define TIMERS34_TIMER_TRIGGER_POINT6 (TIMERS34_BASE + 0x2c)
#define TIMERS34_TIMER_TRIGGER_POINT(n) (TIMERS34_BASE + 0x18 + (n*4) )
#define TIMERS34_TIMER_TRIGGER_CONTROL (TIMERS34_BASE + 0x30)
// UART registers
#define UART1_RBR (UART0_BASE + 0x00) //accessible when DLAB = 0
#define UART1_THR (UART0_BASE + 0x00) //accessible when DLAB = 0
#define UART1_IER (UART0_BASE + 0x04) //accessible when DLAB = 0
#define UART1_IIR (UART0_BASE + 0x08)
#define UART1_FCR (UART0_BASE + 0x08)
#define UART1_LCR (UART0_BASE + 0x0c)
#define UART1_MCR (UART0_BASE + 0x10)
#define UART1_LSR (UART0_BASE + 0x14)
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