jfqs_multiplier.map.eqn

使用加法器树乘法器实现8位乘法运算

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--A1L04Q is product[0]~reg0
--operation mode is normal

A1L04Q_lut_out = c2[0] & c1[0];
A1L04Q = DFFEAS(A1L04Q_lut_out, clock, VCC, , , , , , );


--A1L24Q is product[1]~reg0
--operation mode is normal

A1L24Q_lut_out = E4L1;
A1L24Q = DFFEAS(A1L24Q_lut_out, clock, VCC, , , , , , );


--A1L44Q is product[2]~reg0
--operation mode is normal

A1L44Q_lut_out = F2L1;
A1L44Q = DFFEAS(A1L44Q_lut_out, clock, VCC, , , , , , );


--A1L64Q is product[3]~reg0
--operation mode is normal

A1L64Q_lut_out = F2L3;
A1L64Q = DFFEAS(A1L64Q_lut_out, clock, VCC, , , , , , );


--A1L94Q is product[4]~reg0
--operation mode is arithmetic

A1L94Q_lut_out = F2L5 $ B4L1;
A1L94Q = DFFEAS(A1L94Q_lut_out, clock, VCC, , , , , , );

--A1L84 is product[4]~117
--operation mode is arithmetic

A1L84 = CARRY(F2L5 & B4L1);


--A1L25Q is product[5]~reg0
--operation mode is arithmetic

A1L25Q_carry_eqn = A1L84;
A1L25Q_lut_out = F2L7 $ E2L1 $ A1L25Q_carry_eqn;
A1L25Q = DFFEAS(A1L25Q_lut_out, clock, VCC, , , , , , );

--A1L15 is product[5]~121
--operation mode is arithmetic

A1L15 = CARRY(F2L7 & !E2L1 & !A1L84 # !F2L7 & (!A1L84 # !E2L1));


--A1L55Q is product[6]~reg0
--operation mode is arithmetic

A1L55Q_carry_eqn = A1L15;
A1L55Q_lut_out = F2L9 $ F1L1 $ !A1L55Q_carry_eqn;
A1L55Q = DFFEAS(A1L55Q_lut_out, clock, VCC, , , , , , );

--A1L45 is product[6]~125
--operation mode is arithmetic

A1L45 = CARRY(F2L9 & (F1L1 # !A1L15) # !F2L9 & F1L1 & !A1L15);


--A1L85Q is product[7]~reg0
--operation mode is arithmetic

A1L85Q_carry_eqn = A1L45;
A1L85Q_lut_out = F2L11 $ F1L3 $ A1L85Q_carry_eqn;
A1L85Q = DFFEAS(A1L85Q_lut_out, clock, VCC, , , , , , );

--A1L75 is product[7]~129
--operation mode is arithmetic

A1L75 = CARRY(F2L11 & !F1L3 & !A1L45 # !F2L11 & (!A1L45 # !F1L3));


--A1L16Q is product[8]~reg0
--operation mode is arithmetic

A1L16Q_carry_eqn = A1L75;
A1L16Q_lut_out = F2L31 $ F1L5 $ !A1L16Q_carry_eqn;
A1L16Q = DFFEAS(A1L16Q_lut_out, clock, VCC, , , , , , );

--A1L06 is product[8]~133
--operation mode is arithmetic

A1L06 = CARRY(F2L31 & (F1L5 # !A1L75) # !F2L31 & F1L5 & !A1L75);


--A1L46Q is product[9]~reg0
--operation mode is arithmetic

A1L46Q_carry_eqn = A1L06;
A1L46Q_lut_out = F2L51 $ F1L7 $ A1L46Q_carry_eqn;
A1L46Q = DFFEAS(A1L46Q_lut_out, clock, VCC, , , , , , );

--A1L36 is product[9]~137
--operation mode is arithmetic

A1L36 = CARRY(F2L51 & !F1L7 & !A1L06 # !F2L51 & (!A1L06 # !F1L7));


--A1L76Q is product[10]~reg0
--operation mode is arithmetic

A1L76Q_carry_eqn = A1L36;
A1L76Q_lut_out = F2L71 $ F1L9 $ !A1L76Q_carry_eqn;
A1L76Q = DFFEAS(A1L76Q_lut_out, clock, VCC, , , , , , );

--A1L66 is product[10]~141
--operation mode is arithmetic

A1L66 = CARRY(F2L71 & (F1L9 # !A1L36) # !F2L71 & F1L9 & !A1L36);


--A1L07Q is product[11]~reg0
--operation mode is arithmetic

A1L07Q_carry_eqn = A1L66;
A1L07Q_lut_out = F2L91 $ F1L11 $ A1L07Q_carry_eqn;
A1L07Q = DFFEAS(A1L07Q_lut_out, clock, VCC, , , , , , );

--A1L96 is product[11]~145
--operation mode is arithmetic

A1L96 = CARRY(F2L91 & !F1L11 & !A1L66 # !F2L91 & (!A1L66 # !F1L11));


--A1L37Q is product[12]~reg0
--operation mode is arithmetic

A1L37Q_carry_eqn = A1L96;
A1L37Q_lut_out = F1L31 $ (!A1L37Q_carry_eqn);
A1L37Q = DFFEAS(A1L37Q_lut_out, clock, VCC, , , , , , );

--A1L27 is product[12]~149
--operation mode is arithmetic

A1L27 = CARRY(F1L31 & (!A1L96));


--A1L67Q is product[13]~reg0
--operation mode is arithmetic

A1L67Q_carry_eqn = A1L27;
A1L67Q_lut_out = F1L51 $ (A1L67Q_carry_eqn);
A1L67Q = DFFEAS(A1L67Q_lut_out, clock, VCC, , , , , , );

--A1L57 is product[13]~153
--operation mode is arithmetic

A1L57 = CARRY(!A1L27 # !F1L51);


--A1L97Q is product[14]~reg0
--operation mode is arithmetic

A1L97Q_carry_eqn = A1L57;
A1L97Q_lut_out = F1L71 $ (!A1L97Q_carry_eqn);
A1L97Q = DFFEAS(A1L97Q_lut_out, clock, VCC, , , , , , );

--A1L87 is product[14]~157
--operation mode is arithmetic

A1L87 = CARRY(F1L71 & (!A1L57));


--A1L18Q is product[15]~reg0
--operation mode is normal

A1L18Q_carry_eqn = A1L87;
A1L18Q_lut_out = F1L91 $ (A1L18Q_carry_eqn);
A1L18Q = DFFEAS(A1L18Q_lut_out, clock, VCC, , , , , , );


--c2[0] is c2[0]
--operation mode is normal

c2[0]_lut_out = multiplicand[0];
c2[0] = DFFEAS(c2[0]_lut_out, clock, VCC, , , , , , );


--c1[0] is c1[0]
--operation mode is normal

c1[0]_lut_out = multiplier[0];
c1[0] = DFFEAS(c1[0]_lut_out, clock, VCC, , , , , , );


--E4L1 is add1:U19|add~151
--operation mode is arithmetic

E4L1 = B8L1 $ B7L1;

--E4L2 is add1:U19|add~153
--operation mode is arithmetic

E4L2 = CARRY(B8L1 & B7L1);


--F2L1 is add2:U21|add~226
--operation mode is arithmetic

F2L1 = E4L3 $ B6L1;

--F2L2 is add2:U21|add~228
--operation mode is arithmetic

F2L2 = CARRY(E4L3 & B6L1);


--F2L3 is add2:U21|add~231
--operation mode is arithmetic

F2L3_carry_eqn = F2L2;
F2L3 = E4L5 $ E3L1 $ F2L3_carry_eqn;

--F2L4 is add2:U21|add~233
--operation mode is arithmetic

F2L4 = CARRY(E4L5 & !E3L1 & !F2L2 # !E4L5 & (!F2L2 # !E3L1));


--F2L5 is add2:U21|add~236
--operation mode is arithmetic

F2L5_carry_eqn = F2L4;
F2L5 = E4L7 $ E3L3 $ !F2L5_carry_eqn;

--F2L6 is add2:U21|add~238
--operation mode is arithmetic

F2L6 = CARRY(E4L7 & (E3L3 # !F2L4) # !E4L7 & E3L3 & !F2L4);


--c1[4] is c1[4]
--operation mode is normal

c1[4]_lut_out = multiplier[4];
c1[4] = DFFEAS(c1[4]_lut_out, clock, VCC, , , , , , );


--B4L1 is and_mode:U3|out1[0]~80
--operation mode is normal

B4L1 = c2[0] & c1[4];


--F2L7 is add2:U21|add~241
--operation mode is arithmetic

F2L7_carry_eqn = F2L6;
F2L7 = E4L9 $ E3L5 $ F2L7_carry_eqn;

--F2L8 is add2:U21|add~243
--operation mode is arithmetic

F2L8 = CARRY(E4L9 & !E3L5 & !F2L6 # !E4L9 & (!F2L6 # !E3L5));


--E2L1 is add1:U13|add~151
--operation mode is arithmetic

E2L1 = B4L2 $ B3L1;

--E2L2 is add1:U13|add~153
--operation mode is arithmetic

E2L2 = CARRY(B4L2 & B3L1);


--F2L9 is add2:U21|add~246
--operation mode is arithmetic

F2L9_carry_eqn = F2L8;
F2L9 = E4L11 $ E3L7 $ !F2L9_carry_eqn;

--F2L01 is add2:U21|add~248
--operation mode is arithmetic

F2L01 = CARRY(E4L11 & (E3L7 # !F2L8) # !E4L11 & E3L7 & !F2L8);


--F1L1 is add2:U20|add~213
--operation mode is arithmetic

F1L1 = E2L3 $ B2L1;

--F1L2 is add2:U20|add~215
--operation mode is arithmetic

F1L2 = CARRY(E2L3 & B2L1);


--F2L11 is add2:U21|add~251
--operation mode is arithmetic

F2L11_carry_eqn = F2L01;
F2L11 = E4L31 $ E3L9 $ F2L11_carry_eqn;

--F2L21 is add2:U21|add~253
--operation mode is arithmetic

F2L21 = CARRY(E4L31 & !E3L9 & !F2L01 # !E4L31 & (!F2L01 # !E3L9));


--F1L3 is add2:U20|add~218
--operation mode is arithmetic

F1L3_carry_eqn = F1L2;
F1L3 = E2L5 $ E1L1 $ F1L3_carry_eqn;

--F1L4 is add2:U20|add~220
--operation mode is arithmetic

F1L4 = CARRY(E2L5 & !E1L1 & !F1L2 # !E2L5 & (!F1L2 # !E1L1));


--F2L31 is add2:U21|add~256
--operation mode is arithmetic

F2L31_carry_eqn = F2L21;
F2L31 = E4L51 $ E3L11 $ !F2L31_carry_eqn;

--F2L41 is add2:U21|add~258
--operation mode is arithmetic

F2L41 = CARRY(E4L51 & (E3L11 # !F2L21) # !E4L51 & E3L11 & !F2L21);


--F1L5 is add2:U20|add~223
--operation mode is arithmetic

F1L5_carry_eqn = F1L4;
F1L5 = E2L7 $ E1L3 $ !F1L5_carry_eqn;

--F1L6 is add2:U20|add~225
--operation mode is arithmetic

F1L6 = CARRY(E2L7 & (E1L3 # !F1L4) # !E2L7 & E1L3 & !F1L4);


--F2L51 is add2:U21|add~261
--operation mode is arithmetic

F2L51_carry_eqn = F2L41;
F2L51 = E4L71 $ E3L31 $ F2L51_carry_eqn;

--F2L61 is add2:U21|add~263
--operation mode is arithmetic

F2L61 = CARRY(E4L71 & !E3L31 & !F2L41 # !E4L71 & (!F2L41 # !E3L31));


--F1L7 is add2:U20|add~228
--operation mode is arithmetic

F1L7_carry_eqn = F1L6;
F1L7 = E2L9 $ E1L5 $ F1L7_carry_eqn;

--F1L8 is add2:U20|add~230
--operation mode is arithmetic

F1L8 = CARRY(E2L9 & !E1L5 & !F1L6 # !E2L9 & (!F1L6 # !E1L5));


--F2L71 is add2:U21|add~266
--operation mode is arithmetic

F2L71_carry_eqn = F2L61;
F2L71 = E3L51 $ (!F2L71_carry_eqn);

--F2L81 is add2:U21|add~268
--operation mode is arithmetic

F2L81 = CARRY(E3L51 & (!F2L61));


--F1L9 is add2:U20|add~233
--operation mode is arithmetic

F1L9_carry_eqn = F1L8;
F1L9 = E2L11 $ E1L7 $ !F1L9_carry_eqn;

--F1L01 is add2:U20|add~235
--operation mode is arithmetic

F1L01 = CARRY(E2L11 & (E1L7 # !F1L8) # !E2L11 & E1L7 & !F1L8);


--F2L91 is add2:U21|add~271
--operation mode is normal

F2L91_carry_eqn = F2L81;
F2L91 = E3L71 $ (F2L91_carry_eqn);


--F1L11 is add2:U20|add~238
--operation mode is arithmetic

F1L11_carry_eqn = F1L01;
F1L11 = E2L31 $ E1L9 $ F1L11_carry_eqn;

--F1L21 is add2:U20|add~240
--operation mode is arithmetic

F1L21 = CARRY(E2L31 & !E1L9 & !F1L01 # !E2L31 & (!F1L01 # !E1L9));


--F1L31 is add2:U20|add~243
--operation mode is arithmetic

F1L31_carry_eqn = F1L21;
F1L31 = E2L51 $ E1L11 $ !F1L31_carry_eqn;

--F1L41 is add2:U20|add~245
--operation mode is arithmetic

F1L41 = CARRY(E2L51 & (E1L11 # !F1L21) # !E2L51 & E1L11 & !F1L21);


--F1L51 is add2:U20|add~248
--operation mode is arithmetic

F1L51_carry_eqn = F1L41;
F1L51 = E2L71 $ E1L31 $ F1L51_carry_eqn;

--F1L61 is add2:U20|add~250
--operation mode is arithmetic

F1L61 = CARRY(E2L71 & !E1L31 & !F1L41 # !E2L71 & (!F1L41 # !E1L31));


--F1L71 is add2:U20|add~253
--operation mode is arithmetic

F1L71_carry_eqn = F1L61;
F1L71 = E1L51 $ (!F1L71_carry_eqn);

--F1L81 is add2:U20|add~255
--operation mode is arithmetic

F1L81 = CARRY(E1L51 & (!F1L61));


--F1L91 is add2:U20|add~258
--operation mode is normal

F1L91_carry_eqn = F1L81;
F1L91 = E1L71 $ (F1L91_carry_eqn);


--c2[1] is c2[1]
--operation mode is normal

c2[1]_lut_out = multiplicand[1];
c2[1] = DFFEAS(c2[1]_lut_out, clock, VCC, , , , , , );


--B8L1 is and_mode:U7|out1[1]~80
--operation mode is normal

B8L1 = c1[0] & c2[1];


--c1[1] is c1[1]
--operation mode is normal

c1[1]_lut_out = multiplier[1];
c1[1] = DFFEAS(c1[1]_lut_out, clock, VCC, , , , , , );


--B7L1 is and_mode:U6|out1[0]~73
--operation mode is normal

B7L1 = c2[0] & c1[1];


--E4L3 is add1:U19|add~156
--operation mode is arithmetic

E4L3_carry_eqn = E4L2;
E4L3 = B8L2 $ B7L2 $ E4L3_carry_eqn;

--E4L4 is add1:U19|add~158
--operation mode is arithmetic

E4L4 = CARRY(B8L2 & !B7L2 & !E4L2 # !B8L2 & (!E4L2 # !B7L2));


--c1[2] is c1[2]
--operation mode is normal

c1[2]_lut_out = multiplier[2];
c1[2] = DFFEAS(c1[2]_lut_out, clock, VCC, , , , , , );


--B6L1 is and_mode:U5|out1[0]~80
--operation mode is normal

B6L1 = c2[0] & c1[2];


--E4L5 is add1:U19|add~161
--operation mode is arithmetic

E4L5_carry_eqn = E4L4;
E4L5 = B8L3 $ B7L3 $ !E4L5_carry_eqn;

--E4L6 is add1:U19|add~163
--operation mode is arithmetic

E4L6 = CARRY(B8L3 & (B7L3 # !E4L4) # !B8L3 & B7L3 & !E4L4);


--E3L1 is add1:U16|add~151
--operation mode is arithmetic

E3L1 = B6L2 $ B5L1;

--E3L2 is add1:U16|add~153
--operation mode is arithmetic

E3L2 = CARRY(B6L2 & B5L1);


--E4L7 is add1:U19|add~166
--operation mode is arithmetic

E4L7_carry_eqn = E4L6;
E4L7 = B8L4 $ B7L4 $ E4L7_carry_eqn;

--E4L8 is add1:U19|add~168
--operation mode is arithmetic

E4L8 = CARRY(B8L4 & !B7L4 & !E4L6 # !B8L4 & (!E4L6 # !B7L4));


--E3L3 is add1:U16|add~156
--operation mode is arithmetic

E3L3_carry_eqn = E3L2;
E3L3 = B6L3 $ B5L2 $ E3L3_carry_eqn;

--E3L4 is add1:U16|add~158
--operation mode is arithmetic

E3L4 = CARRY(B6L3 & !B5L2 & !E3L2 # !B6L3 & (!E3L2 # !B5L2));


--E4L9 is add1:U19|add~171
--operation mode is arithmetic

E4L9_carry_eqn = E4L8;
E4L9 = B8L5 $ B7L5 $ !E4L9_carry_eqn;

--E4L01 is add1:U19|add~173
--operation mode is arithmetic

E4L01 = CARRY(B8L5 & (B7L5 # !E4L8) # !B8L5 & B7L5 & !E4L8);


--E3L5 is add1:U16|add~161
--operation mode is arithmetic

E3L5_carry_eqn = E3L4;
E3L5 = B6L4 $ B5L3 $ !E3L5_carry_eqn;

--E3L6 is add1:U16|add~163
--operation mode is arithmetic

E3L6 = CARRY(B6L4 & (B5L3 # !E3L4) # !B6L4 & B5L3 & !E3L4);


--B4L2 is and_mode:U3|out1[1]~81
--operation mode is normal

B4L2 = c1[4] & c2[1];


--c1[5] is c1[5]
--operation mode is normal

c1[5]_lut_out = multiplier[5];
c1[5] = DFFEAS(c1[5]_lut_out, clock, VCC, , , , , , );


--B3L1 is and_mode:U2|out1[0]~73
--operation mode is normal

B3L1 = c2[0] & c1[5];


--E4L11 is add1:U19|add~176
--operation mode is arithmetic

E4L11_carry_eqn = E4L01;
E4L11 = B8L6 $ B7L6 $ E4L11_carry_eqn;

--E4L21 is add1:U19|add~178
--operation mode is arithmetic

E4L21 = CARRY(B8L6 & !B7L6 & !E4L01 # !B8L6 & (!E4L01 # !B7L6));


--E3L7 is add1:U16|add~166
--operation mode is arithmetic

E3L7_carry_eqn = E3L6;
E3L7 = B6L5 $ B5L4 $ E3L7_carry_eqn;

--E3L8 is add1:U16|add~168
--operation mode is arithmetic

E3L8 = CARRY(B6L5 & !B5L4 & !E3L6 # !B6L5 & (!E3L6 # !B5L4));


--E2L3 is add1:U13|add~156
--operation mode is arithmetic

E2L3_carry_eqn = E2L2;
E2L3 = B4L3 $ B3L2 $ E2L3_carry_eqn;

--E2L4 is add1:U13|add~158
--operation mode is arithmetic

E2L4 = CARRY(B4L3 & !B3L2 & !E2L2 # !B4L3 & (!E2L2 # !B3L2));


--c1[6] is c1[6]
--operation mode is normal

c1[6]_lut_out = multiplier[6];
c1[6] = DFFEAS(c1[6]_lut_out, clock, VCC, , , , , , );


--B2L1 is and_mode:U1|out1[0]~80
--operation mode is normal

B2L1 = c2[0] & c1[6];


--E4L31 is add1:U19|add~181
--operation mode is arithmetic

E4L31_carry_eqn = E4L21;
E4L31 = B8L7 $ B7L7 $ !E4L31_carry_eqn;

--E4L41 is add1:U19|add~183
--operation mode is arithmetic

E4L41 = CARRY(B8L7 & (B7L7 # !E4L21) # !B8L7 & B7L7 & !E4L21);


--E3L9 is add1:U16|add~171
--operation mode is arithmetic

E3L9_carry_eqn = E3L8;
E3L9 = B6L6 $ B5L5 $ !E3L9_carry_eqn;

--E3L01 is add1:U16|add~173
--operation mode is arithmetic

E3L01 = CARRY(B6L6 & (B5L5 # !E3L8) # !B6L6 & B5L5 & !E3L8);


--E2L5 is add1:U13|add~161
--operation mode is arithmetic

E2L5_carry_eqn = E2L4;
E2L5 = B4L4 $ B3L3 $ !E2L5_carry_eqn;

--E2L6 is add1:U13|add~163
--operation mode is arithmetic

E2L6 = CARRY(B4L4 & (B3L3 # !E2L4) # !B4L4 & B3L3 & !E2L4);


--E1L1 is add1:U10|add~151
--operation mode is arithmetic

E1L1 = B2L2 $ B1L1;

--E1L2 is add1:U10|add~153
--operation mode is arithmetic

E1L2 = CARRY(B2L2 & B1L1);


--E4L51 is add1:U19|add~186
--operation mode is arithmetic

E4L51_carry_eqn = E4L41;
E4L51 = E4L51_carry_eqn $ (c2[7] & c1[1]);

--E4L61 is add1:U19|add~188
--operation mode is arithmetic

E4L61 = CARRY(!E4L41 # !c1[1] # !c2[7]);


--E3L11 is add1:U16|add~176
--operation mode is arithmetic

E3L11_carry_eqn = E3L01;
E3L11 = B6L7 $ B5L6 $ E3L11_carry_eqn;

--E3L21 is add1:U16|add~178
--operation mode is arithmetic

E3L21 = CARRY(B6L7 & !B5L6 & !E3L01 # !B6L7 & (!E3L01 # !B5L6));


--E2L7 is add1:U13|add~166
--operation mode is arithmetic

E2L7_carry_eqn = E2L6;
E2L7 = B4L5 $ B3L4 $ E2L7_carry_eqn;

--E2L8 is add1:U13|add~168
--operation mode is arithmetic

E2L8 = CARRY(B4L5 & !B3L4 & !E2L6 # !B4L5 & (!E2L6 # !B3L4));


--E1L3 is add1:U10|add~156
--operation mode is arithmetic

E1L3_carry_eqn = E1L2;
E1L3 = B2L3 $ B1L2 $ E1L3_carry_eqn;