📄 _dmul.s
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//****************************************************************************//// _DMUL.S - Routine to multiply two doubles.//// Copyright (c) 1999,2000,2001 Cirrus Logic, Inc.////****************************************************************************#include "../../asmdefs.h"//****************************************************************************//// Read-only code area.////**************************************************************************** _TEXT_//****************************************************************************//// Multiply two doubles.////**************************************************************************** _EXPORT_ _dmul_dmul _LABEL_ stmdb r13!, {r4-r9, r11, r14} movs r12, r2, lsl _CONST_ 1 teqeq r3, _CONST_ 0 mov r8, r12, lsl _CONST_ 10 mov r2, r12, lsr _CONST_ 20 mov r5, r3, lsl _CONST_ 11 orr r4, r8, r3, lsr _CONST_ 21 addne r2, r2, _CONST_ 0x00007800 mov r3, r2, RRX orrne r4, r4, _CONST_ 0x80000000 movs r12, r12, asr _CONST_ 21 addeq r14, pc, _CONST_ 8 beq __fp_norm_op2 cmn r12, _CONST_ 1 beq dmul_uncommon1 movs r12, r0, lsl _CONST_ 1 teqeq r1, _CONST_ 0 mov r8, r12, lsl _CONST_ 10 mov r0, r12, lsr _CONST_ 20 mov r2, r1, lsl _CONST_ 11 orr r1, r8, r1, lsr _CONST_ 21 addne r0, r0, _CONST_ 0x00007800 mov r0, r0, RRX orrne r1, r1, _CONST_ 0x80000000 movs r12, r12, asr _CONST_ 21 addeq r14, pc, _CONST_ 8 beq __fp_norm_op1 cmn r12, _CONST_ 1 beq dmul_uncommon bl __fp_mult_commondmul_return _LABEL_ bl __fp_e2d tst r3, _CONST_ 0x20000000 ldmeqia r13!, {r4-r9, r11, pc} orr r3, r3, _CONST_ 0x00040000 ldmia r13!, {r4-r9, r11, r14}dmul_uncommon1 _LABEL_ orr r3, r3, _CONST_ 0x40000000 movs r12, r0, lsl _CONST_ 1 teqeq r1, _CONST_ 0 mov r8, r12, lsl _CONST_ 10 mov r0, r12, lsr _CONST_ 20 mov r2, r1, lsl _CONST_ 11 orr r1, r8, r1, lsr _CONST_ 21 addne r0, r0, _CONST_ 0x00007800 mov r0, r0, RRX orrne r1, r1, _CONST_ 0x80000000 movs r12, r12, asr _CONST_ 21 addeq r14, pc, _CONST_ 8 beq __fp_norm_op1 cmn r12, _CONST_ 1dmul_uncommon _LABEL_ orreq r0, r0, _CONST_ 0x40000000 adr r14, dmul_return mov r11, _CONST_ 2 b __fp_mult_uncommon__fp_norm_op1 _LABEL_ tst r1, _CONST_ 0x80000000 moveq pc, r14 stmdb r13!, {r3, r14} bics r1, r1, _CONST_ 0x80000000 beq __fp_denorm1_low movs r3, r1, lsr _CONST_ 16 moveq r1, r1, lsl _CONST_ 16 moveq r12, _CONST_ 0x10 movne r12, _CONST_ 0 movs r3, r1, lsr _CONST_ 24 moveq r1, r1, lsl _CONST_ 8 addeq r12, r12, _CONST_ 8 movs r3, r1, lsr _CONST_ 28 moveq r1, r1, lsl _CONST_ 4 addeq r12, r12, _CONST_ 4 movs r3, r1, lsr _CONST_ 30 moveq r1, r1, lsl _CONST_ 2 addeq r12, r12, _CONST_ 2 movs r3, r1, lsr _CONST_ 31 moveq r1, r1, lsl _CONST_ 1 addeq r12, r12, _CONST_ 1 rsb r3, r12, _CONST_ 0x20 orr r1, r1, r2, lsr r3 mov r2, r2, lsl r12 sub r0, r0, r12 add r0, r0, _CONST_ 1 ldmia r13!, {r3, pc}__fp_denorm1_low _LABEL_ movs r3, r2, lsr _CONST_ 16 moveq r2, r2, lsl _CONST_ 16 moveq r12, _CONST_ 0x10 movne r12, _CONST_ 0 movs r3, r2, lsr _CONST_ 24 moveq r2, r2, lsl _CONST_ 8 addeq r12, r12, _CONST_ 8 movs r3, r2, lsr _CONST_ 28 moveq r2, r2, lsl _CONST_ 4 addeq r12, r12, _CONST_ 4 movs r3, r2, lsr _CONST_ 30 moveq r2, r2, lsl _CONST_ 2 addeq r12, r12, _CONST_ 2 movs r3, r2, lsr _CONST_ 31 moveq r2, r2, lsl _CONST_ 1 addeq r12, r12, _CONST_ 1 mov r1, r2 mov r2, _CONST_ 0 sub r0, r0, _CONST_ 0x1f sub r0, r0, r12 ldmia r13!, {r3, pc}__fp_norm_op2 _LABEL_ tst r4, _CONST_ 0x80000000 moveq pc, r14 stmdb r13!, {r0, r14} bics r4, r4, _CONST_ 0x80000000 beq __fp_denorm2_low movs r0, r4, lsr _CONST_ 16 moveq r4, r4, lsl _CONST_ 16 moveq r12, _CONST_ 0x10 movne r12, _CONST_ 0 movs r0, r4, lsr _CONST_ 24 moveq r4, r4, lsl _CONST_ 8 addeq r12, r12, _CONST_ 8 movs r0, r4, lsr _CONST_ 28 moveq r4, r4, lsl _CONST_ 4 addeq r12, r12, _CONST_ 4 movs r0, r4, lsr _CONST_ 30 moveq r4, r4, lsl _CONST_ 2 addeq r12, r12, _CONST_ 2 movs r0, r4, lsr _CONST_ 31 moveq r4, r4, lsl _CONST_ 1 addeq r12, r12, _CONST_ 1 rsb r0, r12, _CONST_ 0x20 orr r4, r4, r5, lsr r0 mov r5, r5, lsl r12 sub r3, r3, r12 add r3, r3, _CONST_ 1 ldmia r13!, {r0, pc}__fp_denorm2_low _LABEL_ movs r0, r5, lsr _CONST_ 16 moveq r5, r5, lsl _CONST_ 16 moveq r12, _CONST_ 0x10 movne r12, _CONST_ 0 movs r0, r5, lsr _CONST_ 24 moveq r5, r5, lsl _CONST_ 8 addeq r12, r12, _CONST_ 8 movs r0, r5, lsr _CONST_ 28 moveq r5, r5, lsl _CONST_ 4 addeq r12, r12, _CONST_ 4 movs r0, r5, lsr _CONST_ 30 moveq r5, r5, lsl _CONST_ 2 addeq r12, r12, _CONST_ 2 movs r0, r5, lsr _CONST_ 31 moveq r5, r5, lsl _CONST_ 1 addeq r12, r12, _CONST_ 1 mov r4, r5 mov r5, _CONST_ 0 sub r3, r3, _CONST_ 0x1f sub r3, r3, r12 ldmia r13!, {r0, pc}__fp_mult_common _LABEL_ bic r8, r0, _CONST_ 0xc0000000 bic r9, r3, _CONST_ 0xc0000000 eor r0, r0, r3 and r0, r0, _CONST_ 0x80000000 add r3, r8, r9 sub r3, r3, _CONST_ 0x3f00 sub r3, r3, _CONST_ 0xfeMult_Mantissas _LABEL_ teq r2, _CONST_ 0 beq Mult_32xXMult_64xX _LABEL_ teq r5, _CONST_ 0 beq Mult_64x32Mult_64x64 _LABEL_ stmdb r13!, {r0, r7, r11, r14} mov r0, r1, lsr _CONST_ 16 bic r7, r1, r0, lsl _CONST_ 16 mov r6, r4, lsr _CONST_ 16 bic r8, r4, r6, lsl _CONST_ 16 mul r9, r0, r6 mul r6, r7, r6 mul r7, r8, r7 adds r7, r7, r6, lsl _CONST_ 16 adc r9, r9, r6, lsr _CONST_ 16 mul r8, r0, r8 adds r7, r7, r8, lsl _CONST_ 16 adc r0, r9, r8, lsr _CONST_ 16 mov r11, r2, lsr _CONST_ 16 bic r14, r2, r11, lsl _CONST_ 16 mov r6, r5, lsr _CONST_ 16 bic r8, r5, r6, lsl _CONST_ 16 mul r9, r11, r6 mul r6, r14, r6 mul r14, r8, r14 adds r14, r14, r6, lsl _CONST_ 16 adc r9, r9, r6, lsr _CONST_ 16 mul r8, r11, r8 adds r14, r14, r8, lsl _CONST_ 16 adc r11, r9, r8, lsr _CONST_ 16 adds r7, r7, r11 adc r0, r0, _CONST_ 0 adds r11, r7, r14 adcs r7, r7, r0 adc r0, r0, _CONST_ 0 subs r8, r1, r2 mov r1, _CONST_ 0 mov r6, _CONST_ 0 mvncc r1, r1 subcc r6, r4, r5 subnes r9, r5, r4 moveq r1, _CONST_ 0 mvncc r1, r1 subcc r6, r6, r8 mov r4, r8, lsr _CONST_ 16 bic r5, r8, r4, lsl _CONST_ 16 mov r8, r9, lsr _CONST_ 16 bic r9, r9, r8, lsl _CONST_ 16 mla r2, r4, r8, r6 mul r8, r5, r8 mul r6, r9, r5 adds r6, r6, r8, lsl _CONST_ 16 adc r2, r2, r8, lsr _CONST_ 16 mul r9, r4, r9 adds r6, r6, r9, lsl _CONST_ 16 adc r2, r2, r9, lsr _CONST_ 16 adds r6, r11, r6 adcs r2, r7, r2 adcs r1, r0, r1 orr r14, r14, r14, lsl _CONST_ 2 orr r6, r6, r14, lsr _CONST_ 2 ldmmiia r13!, {r0, r7, r11, pc} adds r6, r6, r6 adcs r2, r2, r2 adc r1, r1, r1 sub r3, r3, _CONST_ 1 ldmia r13!, {r0, r7, r11, pc}Mult_64x32 _LABEL_ mov r5, r4, lsr _CONST_ 16 bic r6, r4, r5, lsl _CONST_ 16 mov r8, r1, lsr _CONST_ 16 bic r9, r1, r8, lsl _CONST_ 16 mul r4, r5, r8 mul r8, r6, r8 mul r1, r9, r6 adds r1, r1, r8, lsl _CONST_ 16 adc r4, r4, r8, lsr _CONST_ 16 mul r9, r5, r9 adds r1, r1, r9, lsl _CONST_ 16 adc r4, r4, r9, lsr _CONST_ 16 mov r8, r2, lsr _CONST_ 16 bic r9, r2, r8, lsl _CONST_ 16 mul r2, r5, r8 mul r8, r6, r8 mul r6, r9, r6 adds r6, r6, r8, lsl _CONST_ 16 adc r2, r2, r8, lsr _CONST_ 16 mul r9, r5, r9 adds r6, r6, r9, lsl _CONST_ 16 adc r5, r2, r9, lsr _CONST_ 16 adds r2, r5, r1 adcs r1, r4, _CONST_ 0 movmi pc, r14 adds r6, r6, r6 adcs r2, r2, r2 adc r1, r1, r1 sub r3, r3, _CONST_ 1 mov pc, r14Mult_32xX _LABEL_ teq r5, _CONST_ 0 beq Mult_32x32Mult_32x64 _LABEL_ mov r2, r1, lsr _CONST_ 16 bic r6, r1, r2, lsl _CONST_ 16 mov r8, r4, lsr _CONST_ 16 bic r9, r4, r8, lsl _CONST_ 16 mul r1, r2, r8 mul r8, r6, r8 mul r4, r9, r6 adds r4, r4, r8, lsl _CONST_ 16 adc r1, r1, r8, lsr _CONST_ 16 mul r9, r2, r9 adds r4, r4, r9, lsl _CONST_ 16 adc r1, r1, r9, lsr _CONST_ 16 mov r8, r5, lsr _CONST_ 16 bic r9, r5, r8, lsl _CONST_ 16 mul r5, r2, r8 mul r8, r6, r8 mul r6, r9, r6 adds r6, r6, r8, lsl _CONST_ 16 adc r5, r5, r8, lsr _CONST_ 16 mul r9, r2, r9 adds r6, r6, r9, lsl _CONST_ 16 adc r2, r5, r9, lsr _CONST_ 16 adds r2, r2, r4 adcs r1, r1, _CONST_ 0 movmi pc, r14 adds r6, r6, r6 adcs r2, r2, r2 adc r1, r1, r1 sub r3, r3, _CONST_ 1 mov pc, r14__fp_mult_fast_common _LABEL_ bic r8, r0, _CONST_ 0xc0000000 bic r9, r3, _CONST_ 0xc0000000 eor r0, r0, r3 and r0, r0, _CONST_ 0x80000000 add r3, r8, r9 sub r3, r3, _CONST_ 0x3f00 sub r3, r3, _CONST_ 0xfeMult_32x32 _LABEL_ mov r5, r4, lsr _CONST_ 16 bic r6, r4, r5, lsl _CONST_ 16 mov r8, r1, lsr _CONST_ 16 bic r9, r1, r8, lsl _CONST_ 16 mul r1, r5, r8 mul r8, r6, r8 mul r2, r9, r6 adds r2, r2, r8, lsl _CONST_ 16 adc r1, r1, r8, lsr _CONST_ 16 mul r9, r5, r9 adds r2, r2, r9, lsl _CONST_ 16 adcs r1, r1, r9, lsr _CONST_ 16⌨️ 快捷键说明
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