📄 rtxconf.lst
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377 ; Interrupt number to enable-mask table
378 PUBLIC ?RTX_INT_TO_BIT_TABLE_BASE
379
380 ; Greatest interrupt number
381 PUBLIC ?RTX_MAX_INT_NBR
382
383 ; Processor specific interrupt enable masks
384 PUBLIC ?RTX_IE, ?RTX_IEN1, ?RTX_IEN2
385
386 ; Interrupt mask variables
387 PUBLIC ?RTX_NM_IE, ?RTX_D_IE, ?RTX_ND_IE
388 PUBLIC ?RTX_NM_IE1, ?RTX_D_IE1, ?RTX_ND_IE1
389 PUBLIC ?RTX_NM_IE2, ?RTX_D_IE2, ?RTX_ND_IE2
390
391 ; System Timer constants
392 PUBLIC ?RTX_CLK_INT_NBR ; EQUATE
393 PUBLIC ?RTX_TLOW, ?RTX_THIGH, ?RTX_TMOD ; DATA
394 PUBLIC ?RTX_TCON ; DATA
395 PUBLIC ?RTX_TFLAG, ?RTX_TCONTROL ; BIT
396 PUBLIC ?RTX_TMOD_AND_MASK, ?RTX_TMOD_OR_MASK ; EQUATES
397 PUBLIC ?RTX_TCON_AND_MASK, ?RTX_TCON_OR_MASK ; EQUATES
398
399 ; Bank-Switching Support
400 PUBLIC ?RTX_SWITCHBANK ; CODE
401 PUBLIC ?RTX_SAVE_INT_BANK ; DATA
402 IF (?RTX_BANKSWITCHING = 0)
403 PUBLIC ?B_CURRENTBANK ; Dummy DATA-Definition
404 ENDIF
405
406 ; Idle function
407 PUBLIC ?RTX_IDLE_FUNC
408
409 ; Mailbox and semaphore FIFO space
410 PUBLIC ?RTX_MBX_PAGE
411 PUBLIC ?RTX_MBX_PAGE_END
412 PUBLIC ?RTX_SEM_PAGE
413 PUBLIC ?RTX_SEM_PAGE_END
414
415
416 ;*----------------------------------------------------------------------*
417 ;* MACROS
418 ;*----------------------------------------------------------------------*
419
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 05/22/2006 11:27:20 PAGE 7
420 ; This MACRO generates an RTX-51 interrupt entry point using the base
421 ; address ?RTX_INTBASE.
422
423 INT_ENTRY MACRO NO
424 EXTRN XDATA (?RTX_INT&NO&_TID)
425 PUBLIC INT&NO&_VECTOR
426 CSEG AT(?RTX_INTBASE+3+(&NO&*8))
427 INT&NO&_VECTOR: MOV ?RTX_TMP1, A ; Save A
428 MOV A, #LOW(?RTX_INT&NO&_TID); Set up ptr to int. TID
429 LJMP ?RTX_INT_HANDLER ; Jump to general ISR
430 ENDM
431
432
433 ;*----------------------------------------------------------------------*
434 ;* PROCESSOR SPECIFIC DATA DEFINITIONS
435 ;*----------------------------------------------------------------------*
436
ELSEIF (?RTX_CPU_TYPE = 3) ; for upsd3234
584 ;**********
585 ;* Type 3 *
586 ;**********
587 ;------------------------------------------------------------------
588 ; Define the number and addresses of the interrupt enable registers
589 ; 80515/535 -> 2 interrupt enable registers
590 ; (Set the not used registers to the same address as ?RTX_IE)
591
0002 592 INT_EN_MASK_NUMBER EQU 2
00A8 593 ?RTX_IE DATA 0A8H
00A7 594 ?RTX_IEN1 DATA 0A7H ;0B8H
00A8 595 ?RTX_IEN2 DATA 0A8H ; not used
596
597 ;------------------------------------------------------------------
598 ; Generate the interrupt entry points supported by the peripherals
599 ; of the selected CPU type.
600 IF (?RTX_SYSTEM_TIMER = 0)
601 ; Do NOT include the Timer 0 Vector (INT-1)
602 INT_ENTRY 0
609 INT_ENTRY 2
616 INT_ENTRY 3
623 INT_ENTRY 4
630 INT_ENTRY 5
637 INT_ENTRY 8
644 INT_ENTRY 9
651 INT_ENTRY 10
658 INT_ENTRY 11
665 INT_ENTRY 12
672 INT_ENTRY 13
ENDIF
706
707 ;------------------------------------------------------------------
708 ; The following table attaches the interrupt numbers (0..31) to the
709 ; corresponding bits in the interrupt enable masks of the specific
710 ; processor.
711 ; All three interrupt enable register contents must be defined
712 ; for every interrupt number (even when the specific processor contains
713 ; only one interrupt mask).
714 ; Syntax: DB IE-content, IE1-content, IE2-content
715 ;
716 ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
---- 717 RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
718
0000 719 ?RTX_INT_TO_BIT_TABLE_BASE:
0000 010000 720 DB 01H, 00H, 00H ; INT_0 (P3.2/INT0)
0003 020000 721 DB 02H, 00H, 00H ; INT_1 (Timer 0)
0006 040000 722 DB 04H, 00H, 00H ; INT_2 (P3.3/INT1)
0009 080000 723 DB 08H, 00H, 00H ; INT_3 (Timer 1)
000C 100000 724 DB 10H, 00H, 00H ; INT_4 (Serial 1)
000F 200000 725 DB 20H, 00H, 00H ; INT_5 (Timer 2)
0012 000100 726 DB 00H, 01H, 00H ; INT_6 (USB)
0015 008000 727 DB 00H, 80H, 00H ; INT_7 (DDC)
0018 000200 728 DB 00H, 02H, 00H ; INT_8 (IIC)
001B 001000 729 DB 00H, 10H, 00H ; INT_9 (Serial 2)
001E 000000 730 DB 00H, 00H, 00H ; INT_10 not use
0021 000000 731 DB 00H, 00H, 00H ; INT_11 not use
0024 000000 732 DB 00H, 00H, 00H ; INT_12 not use
0027 000000 733 DB 00H, 00H, 00H ; INT_13 not use
734
735 ;------------------------------------------------------------------
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 05/22/2006 11:27:20 PAGE 8
736 ; Define the greatest supported interrupt number
000D 737 ?RTX_MAX_INT_NBR EQU 13
738
0087 739 PCON DATA 87H
740
741 ENTER_IDLE MACRO
742 ;;
743 ;; Enter Idle Mode
744 ;; ---------------
745 ;; To be used whenever entering idle state.
746 ;;
747 ORL PCON, #01H ; Set idle mode (leave by interrupt)
748 ORL PCON, #20H ; (peripherals stay active)
749 ENDM
750
$endif
2395
2396
2397
2398 $eject
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 05/22/2006 11:27:20 PAGE 9
2399 ;*----------------------------------------------------------------------*
2400 ;* DEFINITIONS COMMON FOR ALL PROCESSORS
2401 ;*----------------------------------------------------------------------*
2402
2403 ;------------------------------------------------------------------
2404 ; Define the internal interrupt mask variables. The variables are
2405 ; used for the Interrupt-Handling.
2406 ; Initialise the enable bits for the Interrupt-Enable-Masks
2407 ;
ELSEIF (INT_EN_MASK_NUMBER = 2)
2432 ?RTX?INT_MASK?RTXCONF SEGMENT DATA
---- 2433 RSEG ?RTX?INT_MASK?RTXCONF
2434 ; variables for first mask
0000 2435 ?RTX_NM_IE: DS 1
0001 2436 ?RTX_D_IE: DS 1
0002 2437 ?RTX_ND_IE: DS 1
2438 ; variables for second mask
0003 2439 ?RTX_NM_IE1: DS 1
0004 2440 ?RTX_D_IE1: DS 1
0005 2441 ?RTX_ND_IE1: DS 1
2442 ; variables for third mask (not used)
0006 2443 ?RTX_NM_IE2: DS 0
0006 2444 ?RTX_D_IE2: DS 0
0006 2445 ?RTX_ND_IE2: DS 0
2446
2447 ; RTX-51 calls this routine in the initialisation phase
2448 ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF SEGMENT CODE
---- 2449 RSEG ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF
0000 2450 ?RTX_INIT_INT_REG_FLAGS:
0000 D200 F 2451 SETB ?RTX_ENA_INT_REG1
0002 C200 F 2452 CLR ?RTX_ENA_INT_REG2
0004 22 2453 RET
ENDIF
2478
2479
2480 ;------------------------------------------------------------------
2481 ; Define the System-Timer specific values
2482 ; This values are normally for all 8051 family-members identical.
2483 ;
2484 IF (?RTX_SYSTEM_TIMER = 0)
008A 2485 ?RTX_TLOW DATA 8AH
008C 2486 ?RTX_THIGH DATA 8CH
0088 2487 ?RTX_TCON DATA 88H
0089 2488 ?RTX_TMOD DATA 89H
008D 2489 ?RTX_TFLAG BIT 8DH
008C 2490 ?RTX_TCONTROL BIT 8CH
2491 ; TCON init-masks
2492 ; The clock will be initialized with: ANL TCON, #RTX_TCON_AND_MASK
2493 ; ORL TCON, #RTX_TCON_OR_MASK
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