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📄 main.txt

📁 基于CORTEX-M3内核的stm32f10x芯片的DMA代码
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;;;93       TransferStatus = Buffercmp(SRC_Const_Buffer, DST_Buffer, BufferSize);
0000c8  2220              MOVS     r2,#0x20
0000ca  4921              LDR      r1,|L1.336|
0000cc  481e              LDR      r0,|L1.328|
0000ce  f7fff7ff          BL       Buffercmp
0000d2  4920              LDR      r1,|L1.340|
0000d4  7008              STRB     r0,[r1,#0]  ; TransferStatus
;;;94       /* TransferStatus = PASSED, if the transmitted and received data 
;;;95          are the same */
;;;96       /* TransferStatus = FAILED, if the transmitted and received data 
;;;97          are different */
;;;98       
;;;99       SetupClock();
0000d6  f7fff7ff          BL       SetupClock
;;;100      SetupUART ();
0000da  f7fff7ff          BL       SetupUART
;;;101      for (i=0;i<3000;i++);
0000de  bf00              NOP      
0000e0  e000              B        |L1.228|
                  |L1.226|
0000e2  1c64              ADDS     r4,r4,#1
                  |L1.228|
0000e4  f640f640          MOV      r0,#0xbb8
0000e8  4284              CMP      r4,r0
0000ea  dbfa              BLT      |L1.226|
;;;102      printf ("\r\n Bellow is the data from memory . . .\r\n");
0000ec  a01a              ADR      r0,|L1.344|
0000ee  f7fff7ff          BL       __1printf
;;;103      printf ("\r\n m=%x,endaddr=%x\r\n",m,EndAddr);
0000f2  4a17              LDR      r2,|L1.336|
0000f4  3280              ADDS     r2,r2,#0x80
0000f6  4823              LDR      r0,|L1.388|
0000f8  6801              LDR      r1,[r0,#0]  ; m
0000fa  a023              ADR      r0,|L1.392|
0000fc  f7fff7ff          BL       __1printf
;;;104    
;;;105      printf("\r\n")   ;
000100  a027              ADR      r0,|L1.416|
000102  f7fff7ff          BL       __1printf
;;;106      while( m<( u32 *)EndAddr)
000106  e012              B        |L1.302|
                  |L1.264|
;;;107      {
;;;108        printf("%x",*m);
000108  481e              LDR      r0,|L1.388|
00010a  6800              LDR      r0,[r0,#0]  ; m
00010c  6801              LDR      r1,[r0,#0]
00010e  a025              ADR      r0,|L1.420|
000110  f7fff7ff          BL       __1printf
;;;109        m ++;
000114  481b              LDR      r0,|L1.388|
000116  6800              LDR      r0,[r0,#0]  ; m
000118  1d00              ADDS     r0,r0,#4
00011a  491a              LDR      r1,|L1.388|
00011c  6008              STR      r0,[r1,#0]  ; m
;;;110    	for (i=0;i<30;i++);
00011e  2400              MOVS     r4,#0
000120  e000              B        |L1.292|
                  |L1.290|
000122  1c64              ADDS     r4,r4,#1
                  |L1.292|
000124  2c1e              CMP      r4,#0x1e
000126  dbfc              BLT      |L1.290|
;;;111    	printf ("\t");
000128  a01f              ADR      r0,|L1.424|
00012a  f7fff7ff          BL       __1printf
                  |L1.302|
00012e  4815              LDR      r0,|L1.388|
000130  6801              LDR      r1,[r0,#0]  ; m
000132  4807              LDR      r0,|L1.336|
000134  3080              ADDS     r0,r0,#0x80
000136  4281              CMP      r1,r0
000138  d3e6              BCC      |L1.264|
;;;112      }
;;;113      printf ("\r\n\r\nDMA test is over . DMA test is OK  !  !  !\r\n");
00013a  a01c              ADR      r0,|L1.428|
00013c  f7fff7ff          BL       __1printf
;;;114       while(1)
000140  bf00              NOP      
                  |L1.322|
000142  e7fe              B        |L1.322|
;;;115      {
;;;116      }
;;;117    }
                          ENDP

                  |L1.324|
000144  4002006c          DCD      0x4002006c
                  |L1.328|
000148  00000000          DCD      SRC_Const_Buffer
                  |L1.332|
00014c  00000000          DCD      DMA_InitStructure
                  |L1.336|
000150  00000000          DCD      DST_Buffer
                  |L1.340|
000154  00000000          DCD      TransferStatus
                  |L1.344|
000158  0d0a2042          DCB      "\r\n\40\102"
00015c  656c6c6f          DCB      "ello"
000160  77206973          DCB      "w is"
000164  20746865          DCB      " the"
000168  20646174          DCB      " dat"
00016c  61206672          DCB      "a fr"
000170  6f6d206d          DCB      "om m"
000174  656d6f72          DCB      "emor"
000178  79202e20          DCB      "y . "
00017c  2e202e0d          DCB      ". .\r"
000180  0a000000          DCB      "\n\0\0\0"
                  |L1.388|
000184  00000000          DCD      m
                  |L1.392|
000188  0d0a206d          DCB      "\r\n\40\155"
00018c  3d25782c          DCB      "=%x,"
000190  656e6461          DCB      "enda"
000194  6464723d          DCB      "ddr="
000198  25780d0a          DCB      "%x\r\n"
00019c  00000000          DCB      "\0\0\0\0"
                  |L1.416|
0001a0  0d0a0000          DCB      "\r\n\0\0"
                  |L1.420|
0001a4  25780000          DCB      "%x\0\0"
                  |L1.424|
0001a8  09000000          DCB      "\t\0\0\0"
                  |L1.428|
0001ac  0d0a0d0a          DCB      "\r\n\r\n"
0001b0  444d4120          DCB      "DMA "
0001b4  74657374          DCB      "test"
0001b8  20697320          DCB      " is "
0001bc  6f766572          DCB      "over"
0001c0  202e2044          DCB      " . D"
0001c4  4d412074          DCB      "MA t"
0001c8  65737420          DCB      "est "
0001cc  6973204f          DCB      "is O"
0001d0  4b202021          DCB      "K  !"
0001d4  20202120          DCB      "  ! "
0001d8  20210d0a          DCB      " !\r\n"
0001dc  00000000          DCB      "\0\0\0\0"

                          AREA ||.data||, DATA, ALIGN=2

                  CurrDataCounter_Begin
000000  0000              DCW      0x0000
                  CurrDataCounter_End
000002  0000              DCW      0x0000
                  m
000004  00000000          DCD      DST_Buffer
                  TransferStatus
000008  00                DCB      0x00

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                  SRC_Const_Buffer
000000  01020304          DCD      0x01020304
000004  05060708          DCD      0x05060708
000008  090a0b0c          DCD      0x090a0b0c
00000c  0d0e0f10          DCD      0x0d0e0f10
000010  11121314          DCD      0x11121314
000014  15161718          DCD      0x15161718
000018  191a1b1c          DCD      0x191a1b1c
00001c  1d1e1f20          DCD      0x1d1e1f20
000020  21222324          DCD      0x21222324
000024  25262728          DCD      0x25262728
000028  292a2b2c          DCD      0x292a2b2c
00002c  2d2e2f30          DCD      0x2d2e2f30
000030  31323334          DCD      0x31323334
000034  35363738          DCD      0x35363738
000038  393a3b3c          DCD      0x393a3b3c
00003c  3d3e3f40          DCD      0x3d3e3f40
000040  41424344          DCD      0x41424344
000044  45464748          DCD      0x45464748
000048  494a4b4c          DCD      0x494a4b4c
00004c  4d4e4f50          DCD      0x4d4e4f50
000050  51525354          DCD      0x51525354
000054  55565758          DCD      0x55565758
000058  595a5b5c          DCD      0x595a5b5c
00005c  5d5e5f60          DCD      0x5d5e5f60
000060  61626364          DCD      0x61626364
000064  65666768          DCD      0x65666768
000068  696a6b6c          DCD      0x696a6b6c
00006c  6d6e6f70          DCD      0x6d6e6f70
000070  71727374          DCD      0x71727374
000074  75767778          DCD      0x75767778
000078  797a7b7c          DCD      0x797a7b7c
00007c  7d7e7f80          DCD      0x7d7e7f80

                          AREA ||.bss||, DATA, NOINIT, ALIGN=2

                  DMA_InitStructure
                          %        44
                  DST_Buffer
                          %        128

                  __ARM_use_no_argv EQU 0

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