📄 adc.asm
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;*********************************************************************
; File Name: adc.asm (Version 0.1)
; Project: F240 Peripheral example code suite.
; Originator: Jeff Crankshaw (Texas Instruments)
;
; Target System: F240 EVM (PWB Revision B)
;
; Description: This test configures the ADC for 16 conversions/channel
; for each of the 16 channels (ADCIN0-15). Since the ADC
; is a dual ADC converter, 2 channels (one of ADCIN0-7 and
; one of ADCIN8-15) are converted simulataneously.
;
; The code shows how to configure the ADC for
; simultaneous, continuous conversions using both
; converters. By default, the ADC inputs on the F240
; EVM are floating, so a known voltage will have to
; be applied to each pin to determine the converted value
; matches the applied voltage.
;
; A simple, manual way to test each channel is to tie one
; input to +5V and all other to 0V.
;
; The average converion value for each channel is
; calculated and stored in DARAM block 2. The
; average results are ordered as follows:
;
; 0x70 ADCIN0 average conversion result
; 0x71 ADCIN1 average conversion result
; 0x72 ADCIN2 average conversion result
; 0x73 ADCIN3 average conversion result
; 0x74 ADCIN4 average conversion result
; 0x75 ADCIN5 average conversion result
; 0x76 ADCIN6 average conversion result
; 0x77 ADCIN7 average conversion result
; 0x78 ADCIN8 average conversion result
; 0x79 ADCIN9 average conversion result
; 0x7a ADCIN10 average conversion result
; 0x7b ADCIN11 average conversion result
; 0x7c ADCIN12 average conversion result
; 0x7d ADCIN13 average conversion result
; 0x7e ADCIN14 average conversion result
; 0x7f ADCIN15 average conversion result
;
; All conversion results are stored in DARAM block 0. The
; raw results are ordered as follows:
;
; 0x200-0x20f ADCIN0 conversions 1-16
; 0x210-0x21f ADCIN1 conversions 1-16
; 0x220-0x22f ADCIN2 conversions 1-16
; 0x230-0x23f ADCIN3 conversions 1-16
; 0x240-0x24f ADCIN4 conversions 1-16
; 0x250-0x25f ADCIN5 conversions 1-16
; 0x260-0x26f ADCIN6 conversions 1-16
; 0x270-0x27f ADCIN7 conversions 1-16
; 0x280-0x28f ADCIN8 conversions 1-16
; 0x290-0x29f ADCIN9 conversions 1-16
; 0x2a0-0x2af ADCIN10 conversions 1-16
; 0x2b0-0x2bf ADCIN11 conversions 1-16
; 0x2c0-0x2cf ADCIN12 conversions 1-16
; 0x2d0-0x2df ADCIN13 conversions 1-16
; 0x2e0-0x2ef ADCIN14 conversions 1-16
; 0x2f0-0x2ff ADCIN15 conversions 1-16
;
;
; Status: works.
;
; Last Update: 5 Feb 98
; ____________________________________________________________________
; Date of Mod | DESCRIPTION
; ------------|-------------------------------------------------------
; |
;*********************************************************************
;---------------------------------------------------------------------
; Debug directives
;---------------------------------------------------------------------
.def GPR0 ;General purpose registers.
.def GPR1
.def GPR2
.def GPR3
.def ERROR_REG
.include f240regs.h
;---------------------------------------------------------------------
; Variable Declarations for on chip RAM Blocks
;---------------------------------------------------------------------
.bss GPR0,1 ;General purpose registers.
.bss GPR1,1
.bss GPR2,1
.bss GPR3,1
.bss ERROR_REG,1
;---------------------------------------------------------------------
; M A C R O - Definitions
;---------------------------------------------------------------------
SBIT0 .macro DMA, MASK ;Clear bit Macro
LACC DMA
AND #(0FFFFh-MASK)
SACL DMA
.endm
SBIT1 .macro DMA, MASK ;Set bit Macro
LACC DMA
OR #MASK
SACL DMA
.endm
DELAY_S .macro delay_value ;delay = 0.05uS x delay_value
RPT #delay_value
NOP
.endm
KICK_DOG .macro ;Watchdog reset macro
LDP #00E0h ;DP-->7000h-707Fh
SPLK #055h, WDKEY
SPLK #0AAh, WDKEY
LDP #0h ;DP-->0000h-007Fh
.endm
;---------------------------------------------------------------------
; Vector address declarations
;---------------------------------------------------------------------
.sect ".vectors"
RSVECT B START ; PM 0 Reset Vector 1
INT1 B PHANTOM ; PM 2 Int level 1 4
INT2 B PHANTOM ; PM 4 Int level 2 5
INT3 B PHANTOM ; PM 6 Int level 3 6
INT4 B PHANTOM ; PM 8 Int level 4 7
INT5 B PHANTOM ; PM A Int level 5 8
INT6 B PHANTOM ; PM C Int level 6 9
RESERVED B PHANTOM ; PM E (Analysis Int) 10
SW_INT8 B PHANTOM ; PM 10 User S/W int -
SW_INT9 B PHANTOM ; PM 12 User S/W int -
SW_INT10 B PHANTOM ; PM 14 User S/W int -
SW_INT11 B PHANTOM ; PM 16 User S/W int -
SW_INT12 B PHANTOM ; PM 18 User S/W int -
SW_INT13 B PHANTOM ; PM 1A User S/W int -
SW_INT14 B PHANTOM ; PM 1C User S/W int -
SW_INT15 B PHANTOM ; PM 1E User S/W int -
SW_INT16 B PHANTOM ; PM 20 User S/W int -
TRAP B PHANTOM ; PM 22 Trap vector -
NMI B PHANTOM ; PM 24 Non maskable Int 3
EMU_TRAP B PHANTOM ; PM 26 Emulator Trap 2
SW_INT20 B PHANTOM ; PM 28 User S/W int -
SW_INT21 B PHANTOM ; PM 2A User S/W int -
SW_INT22 B PHANTOM ; PM 2C User S/W int -
SW_INT23 B PHANTOM ; PM 2E User S/W int -
.text
;=====================================================================
; I N I T C O D E - starts here
;=====================================================================
START:
CLRC SXM ; Clear Sign Extension Mode
CLRC OVM ; Reset Overflow Mode
* Set Data Page pointer to page 1 of the peripheral frame
LDP #DP_PF1 ; Page DP_PF1 includes WET through EINT frames
* initialize WDT registers
SPLK #06Fh, WDCR ; clear WDFLAG, Disable WDT, set WDT for 1 second overflow (max)
SPLK #07h, RTICR ; clear RTI Flag, set RTI for 1 second overflow (max)
* configure PLL for 10MHz osc, 10MHz SYSCLK and 20MHz CPUCLK
SPLK #00B1h,CKCR1 ;CLKIN(OSC)=10MHz,CPUCLK=20MHz
SPLK #00C3h,CKCR0 ;CLKMD=PLL Enable,SYSCLK=CPUCLK/2,
* Clear reset flag bits in SYSSR (PORRST, PLLRST, ILLRST, SWRST, WDRST)
LACL SYSSR ; ACCL <= SYSSR
AND #00FFh ; Clear upper 8 bits of SYSSR
SACL SYSSR ; Load new value into SYSSR
* Initialize IOP20/CLKOUT pin for use as DSP clock out
SPLK #40C8h,SYSCR ;No reset, CLKOUT=CPUCLK, VCCA on
* initialize B2 RAM to zero's.
LAR AR1,#B2_SADDR ; AR1 <= B2 start address
MAR *,AR1 ; use B2 start address for next indirect
ZAC ; ACC <= 0
RPT #1fh ; set repeat counter for 1fh+1=20h or 32 loops
SACL *+ ; write zeros to B2 RAM
LDP #0000h
SPLK #4h,GPR3
OUT GPR3,WSGR ;Set XMIF w/no wait states
SPLK #00000h,ERROR_REG ;Clear module error flags
;=====================================================================
; M A I N C O D E - starts here
;=====================================================================
TEST: CALL ADC ;Dummy test for ADC
END B END
;=====================================================================
; Routine Name: ADC Routine Type: Subroutine
; Originator/s: Scott Roller Date: 16 Dec 96
;
; Description: This subroutine tests all 16 channels of the dual
; ADC. Sixteen conversions are performed for each channel.
; These values are then averaged and stored to DARAM block 2.
;
; Variables on Entry on Exit
; --------------------------------------------------------------------
; DP XX 0x0000
; ACC XX XX
; ERROR_REG Error Register Error Register
; --------------------------------------------------------------------
;
; ____________________________________________________________________
; Date of Mod | DESCRIPTION
; ------------|-------------------------------------------------------
; 16 Dec 96 |Created ADC subroutine.
; 10 Apr 97 |Modified ADC subroutine for generic test board
; 5 Feb 98 |Modified ADC subroutine for EVM
; |
;=====================================================================
ADC: KICK_DOG ;Reset WD counter
;=====================================================================
; Initialize Auxilary Registers
;=====================================================================
ADC_INIT: CLRC SXM ;Allow for logical shifts
LAR AR0,#15 ;Set AR0(Loop Counter) to 15
LAR AR1,#B0_SADDR ;AR1 --> ADC_FIFO1 Log
LAR AR2,#B0_SADDR+128 ;AR2 --> ADC_FIFO2 Log
LAR AR3,#7 ;Set AR3(Channel Cntr) to 7
MAR *,AR1 ;ARP=AR1
;=====================================================================
; Initialize ADC Control Registers
;=====================================================================
LDP #00E1h ;DP-->7080h-70FFh
SPLK #0FFFFh, OCRA ;Set IOPA for ADC function
LDP #00E0h ;DP-->7000h-707Fh
SPLK #0000000000000011b, ADCTRL2
; ||||!!!!||||!!!!
; 5432109876543210
;
; bits 15-11: Reserved
; bit 10: Disable EVOC for ADC
; bit 9: Disable EXTSOC for ADC
; bit 8: Reserved
; bits 7-6: ADCFIFO1 Status - Empty
; bit 5: Reserved
; bits 4-3: ADCFIFO2 Status - Empty
; bits 2-0: ADC Prescale of 10
SPLK #0001100110000000b, ADCTRL1
; ||||!!!!||||!!!!
; 5432109876543210
;
; bit 15: Stop conversion before stopping
; bit 14: Stop running on suspend
; bit 13: Do not start ADC conversion immediately
; bit 12: Enable ADC1
; bit 11: Enable ADC2
; bit 10: ADC set for single conversion mode
; bit 9: Disable ADC interrupt requests
; bit 8: Clear Interrupt flag bit
; bit 7: End of ADC conversion - Read only
; bits 6-4: Start Conversion on Channel 9 in ADC2
; bits 3-1: Start Conversion on Channel 1 in ADC1
; bit 0: Do not start conversion
;=====================================================================
; Read conversions from ADC FIFO registers and store values to memory
; Perform 16 conversions on each input.
;=====================================================================
ADC_LOOP: MAR *,AR1
LDP #00E0h ;DP-->7000h-707Fh
STARTNEXT: ; start (or re-start) conversion
LACC ADCTRL1 ;Load ADCTRL1 into ACC
OR #02000h ;Set IM start bit
SACL ADCTRL1 ;Store new value to ADCTRL1
WAIT_EOC: BIT ADCTRL1, BIT7 ;Test for end of conversion
BCND WAIT_EOC, TC ;If not EOC, then loop
LACC ADCFIFO1,10 ;Else,Read ADC1 value
SACH *+,AR2 ;Store ADC1 value to mem.
LACC ADCFIFO2,10 ;Read ADC2 value
SACH *+,AR0 ;Store ADC2 value to mem.
BANZ STARTNEXT,AR1 ;If AR0 > 0, loop
CH_INCR: LAR AR0,#15 ;Reset AR0(Loop Counter) to 15
LDP #00E0h ;DP-->7000h-707Fh
LACC ADCTRL1 ;Load ADCTRL1 into ACC
ADD #0012h ;Increment ADCxCHSEL bits
SACL ADCTRL1 ;Store new value to ADCTRL1
MAR *,AR3 ;Set ARP=AR3, channel loop counter
BANZ STARTNEXT,AR1 ;If all ch's converted,
;fall through loop
;=====================================================================
; Sum and average ADC1 values for all 8 inputs
;=====================================================================
SUM1_INIT: LAR AR1,#B0_SADDR ;AR1 --> ADC_FIFO1 Log
LAR AR3,#7 ;Set AR3(Channel Cntr) to 7
LAR AR2,#B2_SADDR+16 ;AR2 --> ADC_FIFO1 Avg Log
MAR *,AR1 ;ARP=AR1
NXT1_IN: LAR AR0,#14 ;Set AR0(Counter) to 14
LACC *+ ;Load first ADC1 value
ADC1_SUM: ADD *+,AR0 ;Sum ADC1 FIFO values
BANZ ADC1_SUM,AR1 ;If AR0 > 0, loop
RPT #3
SFR ;Divide ADC1 sum by 16
MAR *,AR2
SACL *+,AR3 ;Store avg. value to B2 ram
BANZ NXT1_IN,AR1
;=====================================================================
; Sum and average ADC2 values for all 8 inputs
;=====================================================================
SUM2_INIT: LAR AR2,#B0_SADDR+128 ;AR2 --> ADC_FIFO2 Log
LAR AR3,#7 ;Set AR3(Channel Cntr) to 7
LAR AR1,#B2_SADDR+24 ;AR2 --> ADC_FIFO1 Avg Log
MAR *,AR2 ;ARP=AR2
NXT2_IN: LAR AR0,#14 ;Set AR0(Counter) to 14
LACC *+ ;Load first ADC2 value
ADC2_SUM: ADD *+,AR0 ;Sum ADC2 FIFO values
BANZ ADC2_SUM,AR2 ;If AR0 > 0, loop
RPT #3
SFR ;Divide ADC2 sum by 16
MAR *,AR1
SACL *+,AR3 ;Store avg. value to B2 ram
BANZ NXT2_IN,AR2
ADC_DONE: LDP #0000h ;DP-->0000h-007Fh
RET ;Return from ADC SR
;=====================================================================
; I S R - PHANTOM
;
; Description: Dummy ISR, used to trap spurious interrupts.
;
; Modifies: Nothing
;
; Last Update: 16 June 95
;=====================================================================
PHANTOM KICK_DOG ;Resets WD counter
B PHANTOM
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