alu.asm

lf2407自检源代码

	.title "TMS320C2xx PROCESSOR SELFCHECK -- ALU TEST"
	.length 60
	.width 120
	.option X
************************************************************
*                                                          *
* ALU INSTRUCTIONS TEST                                    *
*                                                          *
* This routine checks ALU operations.                      *
*                                                          *
* Written by David M. Alter                                *
*            member technical staff                        *
*            Texas Instruments Inc.                        *
*                                                          *
* Release Version 1.0                                      *
*                                                          *
************************************************************
	.def    alu
	.nolist
	.copy   "options.h"
	.copy   "memmap.h"
	.list
	
	.text
alu:    .set    $+SS
	
*        
* TEST LOGICAL OPERATIONS
*

;preliminary setup
	LDP     #0h             ;data page @ 0h        
	SPLK    #05454h,TEMP00  ;data(TEMP00) = 5454h
	SPLK    #05151h,TEMP01  ;data(TEMP01) = 5151h
	SPLK    #03333h,TEMP02  ;data(TEMP02) = 3333h
	SPLK    #0aaaah,TEMP03  ;data(TEMP03) = aaaah
	SPLK    #02222h,TEMP04  ;data(TEMP04) = 2222h

;immediate addressing
	LACC    TEMP00          ;ACC = 00005454h        
	OR      #05151h         ;ACC = 00005555h
	XOR     #03333h         ;ACC = 00006666h
	AND     #0aaaah         ;ACC = 00002222h
	SUB     TEMP04          ;ACC = 00002222h
	BCND    eralu1,NEQ      ;if ACC != 0 then error

;immediate addressing with 16 bit shift
	LACC    TEMP00,16       ;ACC = 54540000h
	OR      #05151h,16      ;ACC = 55550000h
	XOR     #03333h,16      ;ACC = 66660000h
	AND     #0aaaah,16      ;ACC = 22220000h
	SACH    TEMP05          ;data(TEMP05)=2222h
	LACC    TEMP05          ;ACC = 00002222h
	SUB     TEMP04          ;ACC = 0
	BCND    eralu1,NEQ      ;if ACC != 0 then error

;direct addressing
	LACC    TEMP00          ;ACC = 00005454h
	OR      TEMP01          ;ACC = 00005555h
	XOR     TEMP02          ;ACC = 00006666h
	AND     TEMP03          ;ACC = 00002222h
	SUB     TEMP04          ;ACC = 0
	BCND    eralu1,NEQ      ;if ACC != 0 then error

;indirect addressing
	LAR     AR0,#TEMP01     ;AR0 points to TEMP01
	MAR     *,AR0           ;ARP --> AR0
	LACC    TEMP00          ;ACC = 00005454h
	OR      *+              ;ACC = 00005555h
	XOR     *+              ;ACC = 00006666h
	AND     *               ;ACC = 00002222h
	SUB     TEMP04          ;ACC = 0     
	BCND    eralu1,NEQ      ;if ACC != 0 then error

*
* TEST ARITHMETIC OPERATIONS
*       

;preliminary setup
	SETC    SXM             ;sign extension mode on
	CLRC    OVM             ;overflow mode off
	SPLK    #0ffffh,TEMP00  ;data(TEMP00) = ffffh
	SPLK    #1h,TEMP01      ;data(TEMP01) = 1h
	LAR     AR0,#TEMP00     ;AR0 points to TEMP01
	LT      TEMP01          ;TREG = 1h                

;primarily addition instructions
	ADD     #0ffffh         ;ACC = ffffffffh
	ADD     TEMP00          ;ACC = fffffffeh
	ADD     *               ;ACC = fffffffdh
	ADDT    TEMP00          ;ACC = fffffffbh
	ADDT    *+              ;ACC = fffffff9h & AR0 points to TEMP01
	ABS                     ;ACC = 7h
	SUB     #7h             ;ACC = 0        
	BCND    eralu2,NEQ      ;if ACC != 0 then error
	
	ADD     #7h             ;ACC = 7h & C=0
	ADD     TEMP00,16       ;ACC = ffff0007h & C=0
	ADD     *,16            ;ACC = 7h & C=1
	ADDC    TEMP01          ;ACC = 9h & C=0
	ADDC    *               ;ACC = ah & C=0
	SUB     #0ah            ;ACC = 0  & C=1
	BCND    alu1,EQ,C       ;branch if ACC=0 & C=1
	B       eralu2          ;branch to error handler

alu1:   .set    $+SS
	CMPL                    ;ACC = ffffffffh
	ADDS    TEMP00          ;ACC = 0000fffeh
	ADDS    *-              ;ACC = 0000ffffh & AR0 points to TEMP00
	XOR     TEMP00          ;ACC = 0
	BCND    eralu2,NEQ      ;if ACC != 0 then error
     
;primarily subtraction operations
	SUB     #0ffffh         ;ACC = 00000001h
	SUB     TEMP00          ;ACC = 00000002h
	SUB     *               ;ACC = 00000003h
	SUBT    TEMP00          ;ACC = 00000005h
	SUBT    *+              ;ACC = 00000007h & AR0 points to TEMP01
	NEG                     ;ACC = fffffff9h
	ADD     #7h             ;ACC = 0
	BCND    eralu3,NEQ      ;if ACC != 0 then error
	
	SUB     #7h             ;ACC = fffffff9h & C=0
	SUB     TEMP00,16       ;ACC = 0000fff9h & C=0
	SUB     *,16            ;ACC = fffffff9h & C=0
	SUBB    TEMP01          ;ACC = fffffff7h & C=1
	SUBB    *               ;ACC = fffffff6h & C=1
	ADD     #0ah            ;ACC = 0 & C=1
	BCND    alu2,EQ,C       ;branch if ACC=0 & C=1
	B       eralu3          ;branch to error handler
alu2:   .set    $+SS
	SUBS    TEMP00          ;ACC = ffff0001h
	SUBS    *               ;ACC = ffff0000h
	XOR     #0ffffh,16      ;ACC = 0
	BCND    eralu3,NEQ      ;if ACC != 0 then error

;test SUBC instruction
	LACL    TEMP00          ;ACC = ffffh
	SFR                     ;ACC = 7fffh
	SUBC    TEMP01          ;ACC = fffeh
	SUBC    *               ;ACC = fffdh
	XOR     #0fffdh         ;ACC = 0
	BCND    eralu4,NEQ      ;if ACC != 0 then error

*
* TEST OVERFLOW MODE OPERATION
*        
	
	SETC    OVM             ;overflow mode on
	CLRC    C               ;clear carry bit
	BCND    alu3,OV         ;force OV bit to clear
alu3:   .set    $+SS
	BCND    eralu5,OV       ;if OV = 1 then error
	LACL    #5h             ;ACC = 5h
	ROR                     ;ACC = 2h & C=1
	ROR                     ;ACC = 80000001h & C=0
	SUB     #2h             ;ACC = 80000000h & OV=1 & C=1
	BCND    eralu5,NOV      ;if OV != 1 then error, & OV=0
	XOR     #8000h,16       ;ACC = 0
	BCND    eralu5,NEQ      ;if ACC != 0 then error
	
	CMPL                    ;ACC = ffffffffh
	XOR     #0a000h,16      ;ACC = 5fffffffh
	ROL                     ;ACC = bfffffffh
	ROL                     ;ACC = 7ffffffeh
	ADD     #2h             ;ACC = 7fffffffh
	BCND    eralu5,NOV      ;if OV != 1 then error, & OV=0
	CMPL                    ;ACC = 80000000h
	XOR     #8000h,16       ;ACC = 0
	BCND    eralu5,NEQ      ;if ACC != 0 then error
	CLRC    OVM             ;overflow mode off

*
* TEST NORM AND ZALR INSTRUCTIONS
*
	
	ZALR    TEMP00          ;ACC = ffff8000h
	CMPL                    ;ACC = 00007fffh
	SUB     #7fffh          ;ACC = 0
	BCND    eralu6,NEQ      ;if ACC != 0 then error
	
	LAR     AR0,#TEMP00     ;AR0 points to TEMP00
	SPLK    #0dfffh,TEMP00  ;data(TEMP00) = dfffh
	CLRC    TC              ;clear TC bit
	NORM    *               ;TC = 1
	BCND    eralu6,NTC      ;if TC != 1 then error
	SAR     AR0,TEMP01      ;data(TEMP01) = stores original AR0
	ZALR    *-              ;ACC = dfff8000h & AR0 = AR0-1
	NORM    *+              ;ACC = bfff0000h & AR0 = AR0+1 & TC=0
	XOR     #0bfffh,16      ;ACC = 0 & pipeline align
	BCND    eralu6,NEQ      ;if ACC != 0 then error & pipeline align
	BCND    eralu6,TC       ;if TC = 1 then error
	SAR     AR0,TEMP02      ;data(TEMP02) = modified AR0
	LACC    TEMP02          ;ACC = modified AR0
	SUB     TEMP01          ;ACC = 0
	BCND    eralu6,NEQ      ;if ACC != 0 then error

	RET                     ;test passes

*
* ERROR HANDLERS
*

eralu1: .set    $+SS
	LACL    #50h            ;ALU logical operations error
	RET                     ;test fails
eralu2: .set    $+SS
	LACL    #51h            ;ALU addition operations error
	RET                     ;test fails
eralu3: .set    $+SS
	LACL    #52h            ;ALU subtraction operations error
	RET                     ;test fails
eralu4: .set    $+SS
	LACL    #53h            ;SUBC instruction error
	RET                     ;test fails
eralu5: .set    $+SS
	LACL    #54h            ;overflow mode error
	RET                     ;test fails
eralu6: .set    $+SS
	LACL    #55h            ;NORM or ZALR error
	RET                     ;test fails