📄 sa5753.lst
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C51 COMPILER V7.02a SA5753 07/08/2003 18:03:11 PAGE 1
C51 COMPILER V7.02a, COMPILATION OF MODULE SA5753
OBJECT MODULE PLACED IN sa5753.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE sa5753.c LARGE OPTIMIZE(0,SPEED) BROWSE DEBUG OBJECTEXTEND TABS(2)
stmt level source
1
2 #include "absacc.h"
3 #include "intrins.h"
4 #include "string.h"
5
6 #include "hand_serial_all_h.h"
7 #include "sa5753_h.h"
8 #include "sa5753_fun_h.h"
9
10
11
12
13 #define SMB_CLK_RATE 80000 //时钟频率
14 #define SMB_CLK_RATE_TIMER -SYSCLK/SMB_CLK_RATE/2+2
15
16 #define WRITE 0x00 // SMBus WRITE command
17 #define READ 0x01 // SMBus READ command
18
19 // SMBus states:
20 // MT = Master Transmitter
21 // MR = Master Receiver
22 #define SMB_BUS_ERROR 0x00 // (all modes) BUS ERROR
23 #define SMB_START 0x08 // (MT & MR) START transmitted
24 #define SMB_MTADDACK 0x18 // (MT) Slave address + W transmitted;
25 // ACK received
26 #define SMB_MTADDNACK 0x20 // (MT) Slave address + W transmitted;
27 // NACK received
28 #define SMB_MTDBACK 0x28 // (MT) data byte transmitted; ACK rec'vd
29 #define SMB_MTDBNACK 0x30 // (MT) data byte transmitted; NACK rec'vd
30 #define SMB_MTARBLOST 0x38 // (MT) arbitration lost
31
32
33 bit SM_BUSY; // This bit is set when a send or receive
34 // is started. It is cleared by the
35 // ISR when the operation is finished.
36 bit g_fist_data_flag; //由于5753数据只有寄存器+数据2个，用单bit判断，如果>2个，用byte判断
37 BYTE idata g_chip_address; //器件地址
38 BYTE idata g_reg_address; //寄存器地址
39 BYTE idata g_reg_data; //寄存器数据
40
41
42 void SM_Send (BYTE chip_select, BYTE address, BYTE out_byte)
43 {
44 1 while (SM_BUSY); // Wait for SMBus to be free.
45 1 SM_BUSY = 1; // Occupy SMBus (set to busy)
46 1 SMB0CN = 0x44; // SMBus enabled, ACK on acknowledge cycle
47 1
48 1 g_fist_data_flag=1; //first数据=寄存器地址
49 1 g_chip_address = (chip_select | WRITE); // 器件地址 + WRITE
50 1 g_reg_address = address; //寄存器地址
51 1 g_reg_data = out_byte; // Data to be writen
52 1
53 1 STA = 1; // Start transfer
54 1
55 1 }
C51 COMPILER V7.02a SA5753 07/08/2003 18:03:11 PAGE 2
56
57 //------------------------------------------------------------------------------------
58 // Interrupt Service Routine
59 //------------------------------------------------------------------------------------
60
61
62 // SMBus interrupt service routine:
63 void SMBUS_ISR (void) interrupt 7 using 2
64 {
65 1 switch (SMB0STA) // Status code for the SMBus (SMB0STA register)
66 1 {
67 2 // Master Transmitter/Receiver: START condition transmitted.
68 2 // The R/W bit of the COMMAND word sent after this state will
69 2 // always be a zero (W) because for both read and write,
70 2 // the memory address must be written first.
71 2 case SMB_START:
72 2 SMB0DAT = g_chip_address; //写器件地址
73 2 STA = 0; // Manually clear START bit
74 2 break;
75 2
76 2 // Master Transmitter: Slave address + WRITE transmitted. ACK received.
77 2 case SMB_MTADDACK:
78 2 SMB0DAT = g_reg_address; //写寄存器地址
79 2 break;
80 2
81 2 // Master Transmitter: Slave address + WRITE transmitted. NACK received.
82 2 // The slave is not responding. Send a STOP followed by a START to try again.
83 2 case SMB_MTADDNACK: //写器件地址后失败
84 2 STO = 1;
85 2 STA = 1;
86 2 // SM_BUSY = 0;
87 2 break;
88 2
89 2 case SMB_MTDBACK: //对多个地址或者数据在这里处理,固定为2个数据，用一个bit判断
90 2 if(_testbit_(g_fist_data_flag))
91 2 {
92 3 SMB0DAT = g_reg_data; // 发送第二个数据
93 3 }
94 2 else //发送完成
95 2 {
96 3 STO = 1;
97 3 SM_BUSY = 0; // Free SMBus
98 3 }
99 2 break;
100 2
101 2 // Master Transmitter: Data byte transmitted. NACK received.
102 2 // Slave not responding. Send STOP followed by START to try again.
103 2 case SMB_MTDBNACK: //写寄存器地址后失败
104 2 STO = 1;
105 2 STA = 1;
106 2 break;
107 2
108 2 // Master Transmitter: Arbitration lost.
109 2 // Should not occur. If so, restart transfer.
110 2 case SMB_MTARBLOST: //仲裁失败
111 2 STO = 1;
112 2 STA = 1;
113 2 break;
114 2
115 2 // All other status codes meaningless in this application. Reset communication.
116 2 default:
117 2 STO = 1; // Reset communication.
C51 COMPILER V7.02a SA5753 07/08/2003 18:03:11 PAGE 3
118 2 SM_BUSY = 0;
119 2 break;
120 2 }
121 1 SI=0; // clear interrupt flag
122 1 }
123
124 void smbus_init(void)
125 {
126 1 SMB0CN = 0x44; // Enable SMBus with ACKs on acknowledge cycle
127 1 SMB0CR = SMB_CLK_RATE_TIMER; // SMBus clock rate = 100kHz.
128 1
129 1 EIE1 |= 2; // SMBus interrupt enable
130 1
131 1 SM_BUSY = 0; // Free SMBus for first transfer.
132 1 }
133
134
135 //#define NOTE_TIME 75 //1/16音符持续时间，按80/分计算 60s/80 = 750ms = 75 *10
136
137 #define NOTE_TIME 100 //1/16音符持续时间，按100/分计算 60s/100 = 1000ms = 100 *10
138
139
140 BYTE xdata g_R0_data;
141 BYTE xdata g_R1_data;
142 BYTE xdata g_R2_data;
143 BYTE xdata g_R3_data;
144 BYTE xdata g_R4_data;
145 BYTE xdata g_R5_data;
146 BYTE xdata g_R6_data;
147 BYTE xdata g_R7_data;
148 BYTE xdata g_R8_data;
149
150 /*
151 ST5753高音值(HD)=1.2M(I2C时钟)/6/频率 范围(778.21Hz to 66.66kHz)
152 ST5753低音值(LD)=1.2M(I2C时钟)/14/频率 范围(333.52Hz to 28.57kHz)
153 因为频率范围不满足音调频率，用高8度频率
154
155 音调 频率（Hz) 高8度频率 高高8度(HD产生) 数组索引 ST5753低音值(FD) ST5753高音值(HD)
156 1 262 *2 524 *2 1 163 0xa3 190
157 2 294 588 2 145 0x91 170
158 3 330 660 3 130 0x82 151
159 4 349 698 4 123 0x7b 143
160 5 392 784 5 109 0x6d 127
161 6 440 880 6 97 0x61 113
162 7 494 998 7 86 0x56 100
163 1^ 523 1046 8 81 0x51 95
164 2^ 1176 9 72 0x48 85
-
165 3^ 1320 a 65 0x41 75
-
166 4^ 1396 b 61 0x3d 71
-
167 5^ 1568 c 54 0x36 63
-
168 5_ 392 d 218 0xda 255
-
169 6_ 440 e 194 0xc2 227
-
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