📄 idwraci2c.asm
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; for specifying the instruction set
; of the target processor
;***********************************************************************
;* TITLE: I2C_asm.ASM
;* AUTHOR: PPG Microcontroller Applications Team
;* DESCRIPTION: Assembly programm that generates an emulated
;* I2C communication between an EEPROM and a ST7
;* describe in the application note AN_1045
;*
;************************************************************************
;***********************************************************************
;* Variables, conSTAnts defined and referenced locally
;* You can define your own values for a local reference here
;***********************************************************************
o_SDA equ P2.3
o_SCL equ P2.4
;***********************I2C_SR1 register*********************************
;#define M_SL 0
;#define ACK 1
;#define RCPT 2
DSEG SADDR
I2C_SR1: DS 1
I2C_SR1_M_SL EQU I2C_SR1.0
I2C_SR1_ACK EQU I2C_SR1.1
I2C_SR1_RCPT EQU I2C_SR1.2
;***********************I2C_SR2 register*********************************
;#define AF 0
I2C_SR2: DS 1
I2C_SR2_AF EQU I2C_SR2.0
;************************************************************************
;* Public routines (defined here)
;************************************************************************/
public SAVEdat
public LOADdat
;========================================================================
t_count_err: DS 1
r_count_err: DS 1
err_STAtus: DS 1
BUFF: DS 1
count: DS 1
I2C_DR: DS 1
D_I2Caddr: DS 1
D_I2Cnum: DS 1
;========================================================================
n_I2Cout equ 10000000B
n_I2Cin equ 10001000B
n_DATAleng EQU 7
;========================================================================
;************************************************************************
;* Module Name: *
;* Function: *
;* Input: *
;* Output: *
;* Break: *
;* STAck: *
;************************************************************************
; History:
;
;------------------------------------------------------------------------
CSEG
;************************************************************************
;* Module Name: CAL_SUM
;* Function: Calculate datas sum
;* Input: X -->Datas length need to cal.
;* Output: A--->Datas sum
;* STAck:
;************************************************************************
CAL_SUM:
LDA #0
MOVW HL,#D_SYSbak-1
CAL_SUM_LOP:
INCW HL
ADD A,[HL]
DEC X
BNE CAL_SUM_LOP
XOR A,#0FFH
; INC A ;ADD A,#1
RET
;------------------------------------------------------------------------
SAVEdat:
BF f_SYStest,$$+4+1
ret
LDX #n_DATAleng
MOVW HL,#F_SYSflag
MOVW DE,#D_SYSbak
BAKlp:
MOV A,[HL]
MOV [DE],A
INCW HL
INCW DE
DEC X
BNE BAKlp
;------------------------------------------------------------------------
;[HIS-001] BUG-01
; BTJF o_COMon,COM3mP
; MOV D_SYSbak+4,#n_3m1s
;COM3mP:
;------------------------------------------------------------------------
LDX #n_DATAleng
CALL !CAL_SUM
CMP A,D_SYSbak+n_DATAleng
BEQ BAKequ
STA D_SYSbak+n_DATAleng
SET1 f_SYSsave
BAKequ:
BBC f_SYSsave,noBAKup1
CLR1 f_SYSsave
mov C_SAVEdelay,#50 ;[his-003]255
noBAKup1:
CMP C_SAVEdelay,#0
BEQ noBAKup
dec C_SAVEdelay
BNE noBAKup
BAKupNOW:
MOVW AX,#D_SYSbak
MOV D_WORK+1,A
XCH A,X
MOV D_WORK,A
LDA #n_DATAleng+1
STA D_I2Cnum
LDA #0
STA D_I2Caddr
CALL !trans
NOP
ret
noBAKup:
call !DELAYA
call !DELAYA
call !DELAYA
RET
DELAYA:
MOV A,#0FFH
nop
nop
nop
nop
nop
nop
DEC A
BNE $-2-2
RET
;************************************************************************
;* Module Name: *
;* Function: *
;* Input: *
;* Output: *
;* Break: *
;* STAck: *
;************************************************************************
; History:
;
;------------------------------------------------------------------------
LOADdat:
MOVW AX,#D_SYSbak
MOV D_WORK+1,A
XCH A,X
STA D_WORK
LDA #n_DATAleng+1
STA D_I2Cnum
LDA #0
STA D_I2Caddr
CALL !recept
restore:
LDX #n_DATAleng
CALL !CAL_SUM
MOVW HL,#D_SYSbak+n_DATAleng
CMP A,[HL]
BZ $$+2+1
RET
; LDX #11 ;#M_MODset-#F_SYSflag
; LDA D_SYSbak+X
; CMP #n_Mheat+1
; BCC $+2+1
; RET
; INC X
; LDA D_SYSbak+X
; CMP #n_FANhigh+1
; BCC $+2+1
; RET
; INC X ;LDA D_SYSbak+#D_TMPset-#F_SYSflag
; LDA D_SYSbak+X
; CMP #30+n_TMPdsp+1
; BCC $+2+1
; RET
; CMP #16+n_TMPdsp
; BCS $+2+1
; RET
LDX #n_DATAleng
MOVW HL,#D_SYSbak
MOVW DE,#F_SYSflag
restoreloop:
MOV A,[HL]
MOV [DE],A
INCW HL
INCW DE
DEC X
BNE restoreloop
mov A,D_TMRset
MOV D_TMRon,A
RET
;************************************************************************
;*-----------------------------------------------------------------------------
;ROUTINE NAME : wait_1ms
;INPUT/OUTPUT : None.
;DESCRIPTION : waiting loop
;-----------------------------------------------------------------------------*/
;wait_1ms:
; LDX #20 ;5
;ag1: LDA #0C6H
;ag: DEC A
; nop ;/*waiting loop of 1ms*/
; BNE ag
; DEC X
; BNE ag1
; RET
;*-----------------------------------------------------------------------------
;ROUTINE NAME : I2Cm_Init
;INPUT/OUTPUT : None.
;DESCRIPTION : I2C peripheral initialisation routine.
;-----------------------------------------------------------------------------*/
I2CInit:
LDA #0
STA count
STA I2C_SR1
STA I2C_SR2
STA I2C_DR
STA err_STAtus
STA t_count_err
STA r_count_err
SET1 I2C_SR1_M_SL ;/*master mode*/
RET
;*-----------------------------------------------------------------------------
;ROUTINE NAME : delay
;INPUT/OUTPUT : None.
;DESCRIPTION : waiting loop
;-----------------------------------------------------------------------------*/
delay:
nop
again:; NOP
DEC A
BNE again ;/* (15+6*time) clock cycles */
RET
;*-----------------------------------------------------------------------------
;ROUTINE NAME : I2Cm_Start
;INPUT/OUTPUT : None.
;DESCRIPTION : Generates I2C-Bus Start Condition.
;-----------------------------------------------------------------------------*/
I2Cm_Start:
NOP
SET1 o_SCL
SET1 o_SDA
LDA #2 ;010H [test]
CALL !delay
CLR1 o_SDA
LDA #2
CALL !delay ;/*waits 39 cycles=4.875祍 at a Fcpu=4Mhz to keep the high STAte on SCL*/
CLR1 o_SCL
LDA #2
CALL !delay ;/*delay to wait after a START*/
RET
;*-----------------------------------------------------------------------------
;ROUTINE NAME : I2Cm_Stop
;INPUT/OUTPUT : None.
;DESCRIPTION : Generates I2C-Bus Stop Condition.
;-----------------------------------------------------------------------------*/
I2Cm_Stop:
LDM PM2,#n_I2Cout ;DA2404 FOR OUTPUT
CLR1 o_SDA ;/*configure SDA and SCL as output open drain to have a low STAte*/
NOP
NOP
NOP
; SET1 PADDR,#SDA ;/*configure SDA and SCL as output open drain to have a low STAte*/
CLR1 o_SCL
NOP
NOP
NOP
SET1 o_SCL
NOP
NOP
NOP
LDA #4
CALL !delay ;/*delay with time=4 (4.875 祍)*/
SET1 o_SDA
RET
;*-----------------------------------------------------------------------------
;ROUTINE NAME : wait_Ack
;INPUT/OUTPUT : None.
;DESCRIPTION : Acknowledge received?
;COMMENTS : Transfer sequence = DATA, ACK.
;-----------------------------------------------------------------------------*/
wait_Ack:
CLR1 o_SCL
NOP
NOP
NOP
NOP
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