cstartup_ads_ram.s

基于Atmel AT91RM9200芯片的bois。使用xmodeom协议与串口通讯。希望大家喜欢

	LDR	r0, =0x2A113154;
	STR	r0, [r1];

	LDR	r1, =AT91C_SDRC_MR;			//0xFFFFFF90
	LDR	r0, =0x00000002;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =AT91C_SDRC_MR;			//0xFFFFFF90
	LDR	r0, =0x00000004;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =AT91C_SDRC_MR;			//0xFFFFFF90
	LDR	r0, =0x00000003;
	STR	r0, [r1];

	LDR	r1, =0x20000080;			//0x20000080
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =AT91C_SDRC_TR;			//0xFFFFFF94
	LDR	r0, =0x000003A8;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =AT91C_SDRC_MR;			//0xFFFFFF90
	LDR	r0, =0;
	STR	r0, [r1];

	LDR	r1, =0x20000000;			//0x20000000
	LDR	r0, =0;
	STR	r0, [r1];
	
;-------------------------
;-	End by zlx 2005.5.13
;-------------------------
	


;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------
;- The processor will remain in the last initialized mode.
;------------------------------------------------------------------------------

;- Load the stack base addresses
	add     r0, pc,#-(8+.-StackData)  ; @ where to read values (relative)
	ldmia   r0, {r1-r6}

;- Set up Supervisor Mode and set SVC Mode Stack
	msr     cpsr_c, #ARM_MODE_SVC:OR:I_BIT:OR:F_BIT
	bic     r1, r1, #3                  ; Insure word alignement
	mov     sp, r1                      ; Init stack SYS

;- Set up Interrupt Mode and set IRQ Mode Stack
	msr     CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
	bic     r2, r2, #3                  ; Insure word alignement
	mov     sp, r2                      ; Init stack IRQ

;- Set up Fast Interrupt Mode and set FIQ Mode Stack
	msr     CPSR_c, #ARM_MODE_FIQ:OR:I_BIT:OR:F_BIT
	bic     r3, r3, #3                  ; Insure word alignement
	mov     sp, r3                      ; Init stack FIQ

;- Set up Abort Mode and set Abort Mode Stack
	msr     CPSR_c, #ARM_MODE_ABORT:OR:I_BIT:OR:F_BIT
	bic     r4, r4, #3                  ; Insure word alignement
	mov     sp, r4                      ; Init stack Abort

;- Set up Undefined Instruction Mode and set Undef Mode Stack
	msr     CPSR_c, #ARM_MODE_UNDEF:OR:I_BIT:OR:F_BIT
	bic     r5, r5, #3                  ; Insure word alignement
	mov     sp, r5                      ; Init stack Undef

;- Set up user Mode and set Undef Mode Stack
	msr     CPSR_c, #ARM_MODE_SYS:OR:I_BIT:OR:F_BIT
	bic     r6, r6, #3                  ; Insure word alignement
	mov     sp, r6                      ; Init stack Undef

	b       EndInitStack

StackData
	DCD     AT91_SVC_Stack_Begin
	DCD     AT91_IRQ_Stack_Begin
	DCD     AT91_FIQ_Stack_Begin
	DCD     AT91_ABT_Stack_Begin
	DCD     AT91_UND_Stack_Begin
	DCD     AT91_USER_Stack_Begin
EndInitStack

;------------------------------------------------------------------------------
;-Low level Init (PMC, AIC, EBI, ....)
;------------------------------------------------------------------------------

;- Add loop to compensate Main Oscillator startup time
	ldr 	r0, =0x00000010
LoopOsc
	subs    r0, r0, #1
	bhi     LoopOsc

	IMPORT    AT91F_LowLevelInit

	ldr       r0, = AT91F_LowLevelInit
	mov       lr, pc
	bx        r0

;----------------------------------------
; Read/modify/write CP15 control register
;----------------------------------------
    MRC     p15, 0, r0, c1, c0,0 ; read cp15 control registre (cp15 r1) in r0
    ldr     r3, =0xC0000080      ; Reset bit :Little Endian end fast bus mode
    ldr     r4, =0xC0000000      ; Set bit :Asynchronous clock mode, Not Fast Bus
    BIC     r0, r0, r3
    ORR     r0, r0, r4
    MCR     p15, 0, r0, c1, c0,0 ; write r0 in cp15 control registre (cp15 r1)

;------------------------------------------------------------------------------
;- Initialise C variables
;------------------------
;- Following labels are automatically generated by the linker.
;- RO: Read-only = the code
;- RW: Read Write = the data pre-initialized and zero-initialized.
;- ZI: Zero-Initialized.
;- Pre-initialization values are located after the code area in the image.
;- Zero-initialized datas are mapped after the pre-initialized.
;- Note on the Data position :
;- If using the ARMSDT, when no -rw-base option is used for the linker, the
;- data area is mapped after the code. You can map the data either in internal
;- SRAM ( -rw-base=0x40 or 0x34) or in external SRAM ( -rw-base=0x2000000 ).
;- Note also that to improve the code density, the pre_initialized data must
;- be limited to a minimum.
;------------------------------------------------------------------------------

	add     r2, pc,#-(8+.-CInitData)  ; @ where to read values (relative)
	ldmia   r2, {r0, r1, r3, r4}

	cmp         r0, r1                  ; Check that they are different
	beq         EndRW
LoopRW
	cmp         r1, r3                  ; Copy init data
	ldrcc       r2, [r0], #4
	strcc       r2, [r1], #4
	bcc         LoopRW
EndRW

	mov         r2, #0
LoopZI
	cmp         r3, r4                  ; Zero init
	strcc       r2, [r3], #4
	bcc         LoopZI

	b           EndInitC

CInitData
 	IMPORT      |Image$$RO$$Limit|      ; End of ROM code (=start of ROM data)
	IMPORT      |Image$$RW$$Base|       ; Base of RAM to initialise
	IMPORT      |Image$$ZI$$Base|       ; Base and limit of area
	IMPORT      |Image$$ZI$$Limit|      ; Top of zero init segment

	DCD     |Image$$RO$$Limit|      ; End of ROM code (=start of ROM data)
 	DCD     |Image$$RW$$Base|       ; Base of RAM to initialise
 	DCD     |Image$$ZI$$Base|       ; Base and limit of area
 	DCD     |Image$$ZI$$Limit|      ; Top of zero init segment
EndInitC


;------------------------------------------------------------------------------
;- Branch on C code Main function (with interworking)
;----------------------------------------------------
;- Branch must be performed by an interworking call as either an ARM or Thumb
;- main C function must be supported. This makes the code not position-
;- independant. A Branch with link would generate errors
;------------------------------------------------------------------------------
	IMPORT      main
_main
__main
	EXPORT    _main
	EXPORT    __main
	ldr       r0, =main
	mov       lr, pc
	bx        r0

;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
End
	b           End



            END