📄 cstartup_ads_ram.s
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;------------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source : cstartup_boot.arm
;- Object : Generic CStartup
;- Compilation flag : None
;-
;- 1.0 23/10/02 FB : Creation ARM ADS
;------------------------------------------------------------------------------
INCLUDE AT91RM9200.inc
;--------------------------------
;- ARM Core Mode and Status Bits
;--------------------------------
ARM_MODE_USER EQU 0x10
ARM_MODE_FIQ EQU 0x11
ARM_MODE_IRQ EQU 0x12
ARM_MODE_SVC EQU 0x13
ARM_MODE_ABORT EQU 0x17
ARM_MODE_UNDEF EQU 0x1B
ARM_MODE_SYS EQU 0x1F
I_BIT EQU 0x80
F_BIT EQU 0x40
T_BIT EQU 0x20
;------------------------------------------------------------------------------
;- Stack Area Definition
;-----------------------
;-
;------------------------------------------------------------------------------
IRQ_STACK_SIZE EQU 0x04
FIQ_STACK_SIZE EQU 0x04
ABT_STACK_SIZE EQU 0x04
UND_STACK_SIZE EQU 0x04
SVC_STACK_SIZE EQU 0x04
USER_STACK_SIZE EQU 0x100
AREA |C$$stack|, DATA
;- IRQ stack definition
AT91_IRQ_Stack_End DCD 0x55AA55AA
SPACE (IRQ_STACK_SIZE - 4)
AT91_IRQ_Stack_Begin EQU (AT91_IRQ_Stack_End + (IRQ_STACK_SIZE - 4))
;- FIQ stack definition
AT91_FIQ_Stack_End DCD 0x55AA55AA
SPACE (FIQ_STACK_SIZE - 4)
AT91_FIQ_Stack_Begin EQU (AT91_FIQ_Stack_End + (FIQ_STACK_SIZE - 4))
;- ABORT stack definition
AT91_ABT_Stack_End DCD 0x55AA55AA
SPACE (ABT_STACK_SIZE - 4)
AT91_ABT_Stack_Begin EQU (AT91_ABT_Stack_End + (ABT_STACK_SIZE - 4))
;- UNDEF stack definition
AT91_UND_Stack_End DCD 0x55AA55AA
SPACE (UND_STACK_SIZE - 4)
AT91_UND_Stack_Begin EQU (AT91_UND_Stack_End + (UND_STACK_SIZE - 4))
;- SVC stack definition
AT91_SVC_Stack_End DCD 0x55AA55AA
SPACE (SVC_STACK_SIZE-4)
AT91_SVC_Stack_Begin EQU (AT91_SVC_Stack_End + (SVC_STACK_SIZE-4))
;- USER and SYSTEM stack definition
AT91_USER_Stack_End DCD 0x55AA55AA
SPACE (USER_STACK_SIZE-4)
AT91_USER_Stack_Begin EQU (AT91_USER_Stack_End + (USER_STACK_SIZE-4))
EXPORT AT91_IRQ_Stack_End
EXPORT AT91_IRQ_Stack_Begin
EXPORT AT91_FIQ_Stack_End
EXPORT AT91_FIQ_Stack_Begin
EXPORT AT91_ABT_Stack_End
EXPORT AT91_ABT_Stack_Begin
EXPORT AT91_UND_Stack_End
EXPORT AT91_UND_Stack_Begin
EXPORT AT91_SVC_Stack_End
EXPORT AT91_SVC_Stack_Begin
EXPORT AT91_USER_Stack_End
EXPORT AT91_USER_Stack_Begin
;------------------------------------------------------------------------------
;- Area Definition
;-----------------
;- Must be defined as function to put first in the code as it must be mapped
;- at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.
;------------------------------------------------------------------------------
AREA reset, CODE, READONLY
; IMPORT __use_no_semihosting_swi
;------------------------------------------------------------------------------
;- Define the entry point
;------------------------
EXPORT __ENTRY
__ENTRY
;------------------------------------------------------------------------------
;- Exception vectors ( before Remap )
;------------------------------------
;- These vectors are read at address 0.
;- They absolutely requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping (what may be
;- dangerous in a final system). If an exception occurs before remap, this
;- would result in an infinite loop.
;------------------------------------------------------------------------------
B InitReset ; reset
undefvec
B undefvec ; Undefined Instruction
swivec
B swivec ; Software Interrupt
pabtvec
B pabtvec ; Prefetch Abort
dabtvec
B dabtvec ; Data Abort
rsvdvec
B rsvdvec ; reserved
irqvec
ldr pc, [pc,#-0xF20] ; IRQ : read the AIC
fiqvec
B fiqvec ; FIQ
;-------------------
;- The reset handler
;-------------------
InitReset
;------------------------------------------------------------------------------
;-PMC initialisation : Enable the Main Oscillator
;------------------------------------------------------------------------------
;-Slow clock mode init
;-After reset, only the 32KHz oscillator is enabled.
;-The ARM7TDMI or ARM9 runs the first instructions at 32768Hz <=> Slow Clock.
;-The processor clock and master clock are enabled at slow clock.
;-All the peripheral clocks are disabled.
;-The main oscillator is disabled.
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;Step 0a.
;------------------------------------------------------------------------------
;-After reset, Slow Clock is normally selected
;-But in case of a boot already started, re-selection of Slow Clock
;-In two steps because of constraints of the Master Clock selection sequence
;-Can be cleared if the project is used for a boot execution
;------------------------------------------------------------------------------
ldr r1, = AT91C_BASE_PMC ; Get the PMC Base Address
;------------------------------------------------------------------------------
;-Write in the MCKR dirty value concerning the clock selection CSS then overwrite it in a second sequence
;------------------------------------------------------------------------------
;-Master Clock Register PMC_MCKR : "dirty CSS" is selected
ldr r0, = AT91C_PMC_CSS_PLLB_CLK
str r0, [r1, #PMC_MCKR]
;- Reading the PMC Status register to detect when the Master Clock is commuted
mov r4, #0x8
MCKR_Loop
ldr r3, [r1, #PMC_SR]
and r3, r4, r3
cmp r3, #0x8
bne MCKR_Loop
;------------------------------------------------------------------------------
;-Second sequence
;------------------------------------------------------------------------------
;-Master Clock Register PMC_MCKR : Slow Clock is selected
ldr r0, = AT91C_PMC_CSS_SLOW_CLK :OR:AT91C_PMC_PRES_CLK
str r0, [r1, #PMC_MCKR]
;- Reading the PMC Status register to detect when the Master Clock is commuted
mov r4, #0x8
MCKR_Loop2
ldr r3, [r1, #PMC_SR]
and r3, r4, r3
cmp r3, #0x8
bne MCKR_Loop2
;------------------------------------------------------------------------------
;Step 0b.
;------------------------------------------------------------------------------
;-After reset,PLLs are disabled
;-But in case of a boot already started, PLLs are turned off
;-Can be cleared if the project is used for a boot execution
;------------------------------------------------------------------------------
ldr r1, = AT91C_BASE_CKGR ; Get the CKGR Base Address
;-Master Clock Register PMC_PLLAR : Turned off PLLA
ldr r0, = AT91C_CKGR_DIVA_0
str r0, [r1, #CKGR_PLLAR]
;-Master Clock Register PMC_PLLBR : Turned off PLLB
ldr r0, = AT91C_CKGR_DIVB_0
str r0, [r1, #CKGR_PLLBR]
;------------------------------------------------------------------------------
;Step 1.
;------------------------------------------------------------------------------
;-Enabling the Main Oscillator
;-Normally First instruction in PMC initialisation
;------------------------------------------------------------------------------
;-Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF
ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT
str r0, [r1, #CKGR_MOR]
;set PIOC as peripheral
LDR r1, =AT91C_PIOC_PDR; //0xFFFFF804
LDR r0, =0xFFFF0000;
STR r0, [r1];
;set EBI cs for sdram
LDR r1, =AT91C_EBI_CSA; //0xFFFFFF60
LDR r0, =0x00000002;
STR r0, [r1];
;Init SDRAM
LDR r1, =AT91C_SDRC_CR; //0xFFFFFF98
; LDR r0, =0x7fffffd0;
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