inst167.a66

TQ公司的STK16x开发系统的源码

		MOV	BUSCON1,R0
$ENDIF

$IF (BUSCON2 = 1)
BCON2		SET     (_MTTC2 << 5) OR (_RWDC2 << 4)
BCON2		SET	BCON2 OR ((NOT _MCTC2) AND 0FH)
BCON2		SET	BCON2 AND (NOT (_RDYEN2 << 3))
BCON2 		SET	BCON2 OR (_RDY_AS2 << 3)  OR (_BTYP2 << 6)
BCON2 		SET	BCON2 OR (_ALECTL2 << 9) OR (_BUSACT2 << 10)
BCON2		SET	BCON2 OR (_RDYEN2 << 12) OR (_CSREN2 << 14)
BCON2           SET     BCON2 OR (_CSWEN2 << 15)

%ADDR (ADDR2,%ADDRESS2,%RANGE2)
		MOV	ADDRSEL2,#ADDR2 
		MOV	BUSCON2,#BCON2
$ENDIF

$IF (BUSCON3 = 1)
BCON3		SET     (_MTTC3 << 5) OR (_RWDC3 << 4)
BCON3		SET	BCON3 OR ((NOT _MCTC3) AND 0FH)
BCON3		SET	BCON3 AND (NOT (_RDYEN3 << 3))
BCON3 		SET	BCON3 OR (_RDY_AS3 << 3)  OR (_BTYP3 << 6)
BCON3 		SET	BCON3 OR (_ALECTL3 << 9) OR (_BUSACT3 << 10)
BCON3		SET	BCON3 OR (_RDYEN3 << 12) OR (_CSREN3 << 14)
BCON3           SET     BCON3 OR (_CSWEN3 << 15)

%ADDR (ADDR3,%ADDRESS3,%RANGE3)
		MOV	ADDRSEL3,#ADDR3 
		MOV	BUSCON3,#BCON3
$ENDIF

$IF (BUSCON4 = 1)
BCON4		SET     (_MTTC4 << 5) OR (_RWDC4 << 4)
BCON4		SET	BCON4 OR ((NOT _MCTC4) AND 0FH)
BCON4		SET	BCON4 AND (NOT (_RDYEN4 << 3))
BCON4 		SET	BCON4 OR (_RDY_AS4 << 3)  OR (_BTYP4 << 6)
BCON4 		SET	BCON4 OR (_ALECTL4 << 9) OR (_BUSACT4 << 10)
BCON4		SET	BCON4 OR (_RDYEN4 << 12) OR (_CSREN4 << 14)
BCON4           SET     BCON4 OR (_CSWEN4 << 15)

%ADDR (ADDR4,%ADDRESS4,%RANGE4)
		MOV	ADDRSEL4,#ADDR4 
		MOV	BUSCON4,#BCON4
$ENDIF
$IF (STK_SIZE = 7)
		MOV	STKUN,#0FFFEH		; AVOID STKUN TRAP
		MOV	STKOV,#0H		; AVOID STKOV TRAP
$ENDIF
                EINIT
$ENDIF

$IF SERIAL0
;********************************************************************
;*  Initialization of Serial Interface 0                            *
;********************************************************************


$IF NOT (BOOTSTRAP)	        ; skip initialization when using bootstrap loader
	BSET	P3.10		; SET PORT 3.10 OUTPUT LATCH (TXD)
	BSET	DP3.10		; SET PORT 3.10 DIRECTION CONTROL (TXD OUTPUT)
	BCLR	DP3.11		; RESET PORT 3.11 DIRECTION CONTROL (RXD INPUT)
	MOVB	S0TIC,#080H	; SET TRANSMIT INTERRUPT FLAG
	MOVB	S0RIC,#000H	; DELETE RECEIVE INTERRUPT FLAG
IF (BAUDRATE = 0)
; Auto adjust Baudrate
WStrtB:
        JB	P3.11,WStrtB    ; wait for start bit at RXD0
        BSET	T3R		; start timer T3
WStpB:  JNB	P3.11,WStpB	; wait for stop bit at RXD0
        BCLR	T3R		; stop timer T3
        MOV	MDL,T3
        SUB	MDL,#18		; rounding & adjustment
        MOV	R1,#36		; baudrate = (T3 / 36) - 1
        DIVU	R1
        MOV	S0BG,MDL	; load baudrate generator
	MOV	S0CON,#8011H	; SET SERIAL MODE
        MOV	T3,#0		; Clear timer 3 register
        MOV	S0TBUF,#0FFH    ; Send acknoledge byte for monitor
ELSE 
; Fixed Baudrate
;BG_RLOAD EQU (CPU_CLOCK / (32 * BAUDRATE)) - 1 
BG_RLOAD EQU ((CPU_CLOCK / (16 * BAUDRATE)) - 1)/2
	MOV	S0BG ,#BG_RLOAD	; SET BAUDRATE
        MOV	S0CON,#8011H	; SET SERIAL MODE
ENDIF
$ENDIF
	JMP	CC_UC,MON166


;********************************************************************
;*  Basic Input Output Functions for serial Interface 0             *
;********************************************************************

INSTAT:		BMOV	R4.0,S0RIR	; INPUT STATUS OF SERIAL INTERFACE
		RET

OUTSTAT:	BMOV	R4.0,S0TIR	; OUTPUT STATUS OF SERIAL INTERFACE
		RET

INCHAR:		MOV	R4,S0RBUF	; CHARACTER INPUT-ROUTINE 
		RET

OUTCHAR:	MOV	S0TBUF,R4	; CHARACTER OUTPUT-ROUTINE 
		RET

CLR_TI:		BCLR	S0TIR		; CLEAR SERIAL TRANSMIT INTERRUPT FLAG
		RET

SET_TI:		BSET	S0TIR		; SET SERIAL TRANSMIT INTERRUPT FLAG
		RET

CLR_RI:		BCLR	S0RIR		; CLEAR SERIAL RECEIVE INTERRUPT FLAG
		RET

CLR_SER_IE:	MOV	S0RIC,#0000	; CLR S0RIE AND ILVL=0
		RET

SET_SER_IE:	MOV	S0RIC,#007CH	; SET S0RIE AND ILVL=15
		RET

RD_RIE:		BMOV	R4.0,S0RIE	; READ RECEIVE INTERRUPT ENABLE FLAG
		RET

RD_TIE:		BMOV	R4.0,S0TIE	; READ TRANSMIT INTERRUPT ENABLE FLAG
		RET

WR_RIE:		BMOV	S0RIE,R4.0	; WRITE RECEIVE INTERRUPT ENABLE FLAG
		RET

WR_TIE:		BMOV	S0TIE,R4.0	; WRITE TRANSMIT INTERRUPT ENABLE FLAG
		RET

WR_RIR:		BMOV	S0RIR,R4.0	; WRITE RECEIVE INTERRUPT ENABLE FLAG
		RET

WR_TIR:		BMOV	S0TIR,R4.0	; WRITE TRANSMIT INTERRUPT ENABLE FLAG
		RET

BEFORE_GO:				; IS NOT USED
		RET

AFTER_GO:				; IS NOT USED
		RET
$ENDIF


$IF (SERIAL2)
;********************************************************************
;*  Initialization of simulated Serial Interface 2                  *
;********************************************************************

T_LINE          BIT     P2.0            ; Transmit Data Line TxD
T_OUT           BIT     DP2.0           ; Port direction register for TxD
R_LINE          BIT     P2.1            ; Receive Data Line RxD
R_IN            BIT     DP2.1           ; Port direction register for RxD


STATES_PER_BIT	EQU	(CPU_CLOCK / BAUDRATE)

         	BSET    T_LINE          ;          
        	BSET    T_OUT           ; set TxD to output
        	BCLR    R_IN            ; set RxD to input
		CALL    AFTER_GO

		JMP	CC_UC,MON166


INSTAT:		BSET	R4.0		; INPUT STATUS OF SERIAL INTERFACE
		RET

OUTSTAT:	BSET	R4.0		; OUTPUT STATUS OF SERIAL INTERFACE
		RET




;*************** CHARACTER INPUT-ROUTINE ************************

INCHAR:		PUSH	R2		
                PUSH    R3
                MOV     R3,#8           ; Bit counter
                MOV     R4,#00H
              
STARTBIT:       JNB     R_LINE,STARTBIT ; Wait until last data bit is over
STARTBIT1:      JB      R_LINE,STARTBIT1; Wait for startbit
		MOV	R2,DPP0:C_VAR1	; Startbit valid, begin sampling !
WAIT1:   	SUB	R2,#1           ;
		JMPR	CC_NZ,WAIT1     ;  
RECEIVE:	BMOV	R4.8,R_LINE     ; Bit input
		SHR	R4,#1
		SUB	R3,#1
		JMPR	CC_Z,LASTBIT    ; Last bit ?

		MOV     R2,DPP0:C_VAR2  ; Sample period generation
WAIT2:		SUB	R2,#1
		JMPR	CC_NZ,WAIT2
		JMPR	CC_UC,RECEIVE

LASTBIT:        POP     R3              
		POP	R2
		RET



;*************** CHARACTER OUTPUT-ROUTINE *******************

OUTCHAR:	PUSH	R2
                PUSH    R3
                PUSH    R4
		OR	R4,#0100H	; Insert stopbit 
		SHL	R4,#1           ; Insert startbit
                MOV     R3,#10          ; Bit counter

NEXTBIT:	ASHR	R4,#1
		BMOV	T_LINE,C	; Bit output

		MOV	R2,DPP0:C_VAR3
WAIT:		SUB	R2,#1
		JMPR	CC_NZ,WAIT	; Baud rate generation

                SUB     R3,#1
                JMPR    CC_NZ,NEXTBIT   ; Last bit ? 

                POP     R4              ; Yes  
                POP     R3
		POP	R2
		RET

CLR_TI:		RET			; IS NOT USED

SET_TI:		RET			; IS NOT USED

CLR_RI:		RET			; IS NOT USED

CLR_SER_IE:	RET			; IS NOT USED

SET_SER_IE:	RET			; IS NOT USED

RD_RIE:		RET			; IS NOT USED

RD_TIE:		RET			; IS NOT USED

WR_RIE:		RET			; IS NOT USED

WR_TIE:		RET			; IS NOT USED

WR_RIR:		RET			; IS NOT USED

WR_TIR:		RET			; IS NOT USED

BEFORE_GO:	RET			; IS NOT USED


AFTER_GO:	MOV	DPP0,#PAG MON166_W_DATA
 		MOV	R1,DPP3:BUSCON0       ; Programmed number of waitstates
		AND	R1,#000FH         
		MOV	R2,#15
		SUB	R2,R1                 ; ACT = State times for one
		ADD	R2,#3                 ; external memory access
		MOV	R1,DPP3:BUSCON0
		SHR	R1,#5
		AND	R1,#0001H
		SUB	R2,R1
		JNB	BUSCON0.6,NMBUS
		ADD	R2,#1                 ; Multiplexed bus
 
NMBUS:		MOV	R3,#14                ; Non-multiplexed bus 
		JB	BUSCON0.7,BIT_16_1
		ADD	R3,#13                ; 8-Bit bus    (16 ACTs)
BIT_16_1:	MOV	R13,#STATES_PER_BIT   ; 16-Bit bus   (8  ACTs) 
		MUL	R3,R2                 ;
		SUB	R13,MDL
		SUB	R13,#4     
		SHR	R13,#2                ; Remaining states for loop
		MOV	DPP0:C_VAR2,R13

		MOV	R13,#STATES_PER_BIT   ; Multiply by 1.5
		MOV	R3,R13
		SHR	R3,#1
		ADD	R13,R3

		MOV	R3,#11
		JB	BUSCON0.7,BIT_16_2
		ADD	R3,#14;               ; 8-Bit Bus
BIT_16_2:	MUL	R3,R2
		SUB	R13,MDL
		SUB	R13,#2
		SHR	R13,#2
		MOV	DPP0:C_VAR1,R13

		MOV	R13,#STATES_PER_BIT
		MOV	R3,#13
		JB	BUSCON0.7,BIT_16_3
		ADD	R3,#10                ; 8-Bit Bus
BIT_16_3:	MUL	R3,R2
		SUB	R13,MDL
		SUB	R13,#4
		SHR	R13,#2
		MOV	DPP0:C_VAR3,R13		
		RET

$ENDIF

INSTALLCODE	ENDP
INIT_CODE	ENDS

		END