📄 configv2.inc
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;
; Definitions for Address Select register ADDRSEL4
; ================================================
;
_ADDR4 EQU 0xA00000 ; Set CS4# Start Address (default 400000H)
;
_SIZE4 EQU 1*MB ; Set CS4# Size (default 1024*KB = 1*MB)
; possible values for _SIZE4 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS4
; =======================================================
;
; ENCS4: Enable Chip Select (FCONCS4.0)
_ENCS4 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; RDYEN4: Ready Enable (FCONCS4.1)
_RDYEN4 EQU 0 ; 0 = Access time controlled by TCONCS4.PHE4
; 1 = Access time cont. by TCONCS4.PHE4 and READY signal
;
; RDYMOD4: Ready Mode (FCONCS4.2)
_RDYMOD4 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; BTYP4: Bus Type Selection (FCONCS4.4 .. FCONCS4.5)
_BTYP4 EQU 0 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS4: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA4: Phase A clock cycle (TCONCS4.0 .. TCONCS4.1)
_PHA4 EQU 1 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHB4: Phase B clock cycle (TCONCS4.2)
_PHB4 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; PHC4: Phase C clock cycle (TCONCS4.3 .. TCONCS4.4)
_PHC4 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHD4: Phase D clock cycle (TCONCS4.5)
_PHD4 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; PHE4: Phase E clock cycle (TCONCS4.6 .. TCONCS4.10)
_PHE4 EQU 2 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; RDPHF4: Phase F read clock cycle (TCONCS4.11 .. TCONCS4.12)
_RDPHF4 EQU 1 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; WRPHF4: Phase F write clock cycle (TCONCS4.13 .. TCONCS4.14)
_WRPHF4 EQU 1 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS5 AREA ===========
;
; --- Set CONFIG_CS5 = 1 to initialize the ADDRSEL5/FCONCS5/TCONCS5 registers
$SET (CONFIG_CS5 = 0)
;
; Definitions for Address Select register ADDRSEL5
; ================================================
;
_ADDR5 EQU 0xB00000 ; Set CS5# Start Address (default 500000H)
;
_SIZE5 EQU 1*MB ; Set CS5# Size (default 1024*KB = 1*MB)
; possible values for _SIZE5 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS5
; =======================================================
;
; ENCS5: Enable Chip Select (FCONCS5.0)
_ENCS5 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; RDYEN5: Ready Enable (FCONCS5.1)
_RDYEN5 EQU 0 ; 0 = Access time controlled by TCONCS5.PHE5
; 1 = Access time cont. by TCONCS5.PHE5 and READY signal
;
; RDYMOD5: Ready Mode (FCONCS5.2)
_RDYMOD5 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; BTYP5: Bus Type Selection (FCONCS5.4 .. FCONCS5.5)
_BTYP5 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS5: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA5: Phase A clock cycle (TCONCS5.0 .. TCONCS5.1)
_PHA5 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHB5: Phase B clock cycle (TCONCS5.2)
_PHB5 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; PHC5: Phase C clock cycle (TCONCS5.3 .. TCONCS5.4)
_PHC5 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHD5: Phase D clock cycle (TCONCS5.5)
_PHD5 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; PHE5: Phase E clock cycle (TCONCS5.6 .. TCONCS5.10)
_PHE5 EQU 9 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; RDPHF5: Phase F read clock cycle (TCONCS5.11 .. TCONCS5.12)
_RDPHF5 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; WRPHF5: Phase F write clock cycle (TCONCS5.13 .. TCONCS5.14)
_WRPHF5 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS6 AREA ===========
;
; --- Set CONFIG_CS6 = 1 to initialize the ADDRSEL6/FCONCS6/TCONCS6 registers
$SET (CONFIG_CS6 = 0)
;
; Definitions for Address Select register ADDRSEL6
; ================================================
;
_ADDR6 EQU 0xB00000 ; Set CS6# Start Address (default 600000H)
;
_SIZE6 EQU 1*MB ; Set CS6# Size (default 1024*KB = 1*MB)
; possible values for _SIZE6 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS6
; =======================================================
;
; ENCS6: Enable Chip Select (FCONCS6.0)
_ENCS6 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; RDYEN6: Ready Enable (FCONCS6.1)
_RDYEN6 EQU 0 ; 0 = Access time controlled by TCONCS6.PHE6
; 1 = Access time cont. by TCONCS6.PHE6 and READY signal
;
; RDYMOD6: Ready Mode (FCONCS6.2)
_RDYMOD6 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; BTYP6: Bus Type Selection (FCONCS6.4 .. FCONCS6.5)
_BTYP6 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS6: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA6: Phase A clock cycle (TCONCS6.0 .. TCONCS6.1)
_PHA6 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHB6: Phase B clock cycle (TCONCS6.2)
_PHB6 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; PHC6: Phase C clock cycle (TCONCS6.3 .. TCONCS6.4)
_PHC6 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHD6: Phase D clock cycle (TCONCS6.5)
_PHD6 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; PHE6: Phase E clock cycle (TCONCS6.6 .. TCONCS6.10)
_PHE6 EQU 9 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; RDPHF6: Phase F read clock cycle (TCONCS6.11 .. TCONCS6.12)
_RDPHF6 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; WRPHF6: Phase F write clock cycle (TCONCS6.13 .. TCONCS6.14)
_WRPHF6 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS7 AREA ===========
;
; --- Set CONFIG_CS7 = 1 to initialize the ADDRSEL7/FCONCS7/TCONCS7 registers
; --- Note: The CS7# chip default at reset allows to access the on-chip Twin-CAN
$SET (CONFIG_CS7 = 0)
;
; Definitions for Address Select register ADDRSEL7
; ================================================
;
_ADDR7 EQU 0x200000 ; Set CS7# Start Address (default 200000H)
;
_SIZE7 EQU 4*KB ; Set CS7# Size (default 1024*KB = 1*MB)
; possible values for _SIZE7 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS7
; =======================================================
;
; ENCS7: Enable Chip Select (FCONCS7.0)
_ENCS7 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; RDYEN7: Ready Enable (FCONCS7.1)
_RDYEN7 EQU 1 ; 0 = Access time controlled by TCONCS7.PHE7
; 1 = Access time cont. by TCONCS7.PHE7 and READY signal
;
; RDYMOD7: Ready Mode (FCONCS7.2)
_RDYMOD7 EQU 1 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; BTYP7: Bus Type Selection (FCONCS7.4 .. FCONCS7.5)
_BTYP7 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS7: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA7: Phase A clock cycle (TCONCS7.0 .. TCONCS7.1)
_PHA7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHB7: Phase B clock cycle (TCONCS7.2)
_PHB7 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; PHC7: Phase C clock cycle (TCONCS7.3 .. TCONCS7.4)
_PHC7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHD7: Phase D clock cycle (TCONCS7.5)
_PHD7 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; PHE7: Phase E clock cycle (TCONCS7.6 .. TCONCS7.10)
_PHE7 EQU 0 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; RDPHF7: Phase F read clock cycle (TCONCS7.11 .. TCONCS7.12)
_RDPHF7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; WRPHF7: Phase F write clock cycle (TCONCS7.13 .. TCONCS7.14)
_WRPHF7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;------------------------------------------------------------------------------
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