configv2.inc

TQ公司的STK16x开发系统的源码

;
;
; Definitions for EBC Mode 1 register EBCMOD1
; ===========================================
;
; APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD0.4)
_APDIS     EQU    0     ; 0  = Address port PORT1 used as address bus
                        ; 1 - 30 = reserved
                        ; 31 = Address bus disabled (PORT1 used as GPIO)
;
; DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
_DHPDIS    EQU    0     ; 0 = Data bus pins 15-8 of PORT0 enabled
                        ; 1 = Data bus pins 15-8 disabled (used as GPIO)
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS0 AREA ===========
;
; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
$SET (CONFIG_CS0 = 1)
;
; Definitions for Function Configuration Register FCONCS0
; =======================================================
;
; ENCS0: Enable Chip Select (FCONCS0.0)
_ENCS0     EQU    1     ; 0 = Chip Select 0 disabled
                        ; 1 = Chip Select 0 enabled
;
; RDYEN0: Ready Enable (FCONCS0.1)
_RDYEN0    EQU    0     ; 0 = Access time controlled by TCONCS0.PHE0
                        ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
;
; RDYMOD0: Ready Mode (FCONCS0.2)
_RDYMOD0   EQU    0     ; 0 = Asynchronous READY
                        ; 1 = Synchronous READY
;
; BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
_BTYP0     EQU    2     ; 0 = 8 bit Demultiplexed bus
                        ; 1 = 8 bit Multiplexed bus
                        ; 2 = 16 bit Demultiplexed bus
                        ; 3 = 16 bit Multiplexed bus
;
;
; TCONCS0: Definitions for the Timing Configuration register 
; ==========================================================
;
; PHA0: Phase A clock cycle (TCONCS0.0 .. TCONCS0.1)
_PHA0       EQU    1    ; 0 = 0 clock cycles
                        ; : = : 
                        ; 3 = 3 clock cycles
;
; PHB0: Phase B clock cycle (TCONCS0.2)
_PHB0       EQU    0    ; 0 = 1 clock cycle
                        ; 1 = 2 clock cycles
;
; PHC0: Phase C clock cycle (TCONCS0.3 .. TCONCS0.4)
_PHC0       EQU    1    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; PHD0: Phase D clock cycle (TCONCS0.5)
_PHD0       EQU    0    ; 0 = 0 clock cycles
                        ; 1 = 1 clock cycle
;
; PHE0: Phase E clock cycle (TCONCS0.6 .. TCONCS0.10)
_PHE0       EQU    3    ; 0 = 1 clock cycle
                        ; : = :
                        ; 31 = 32 clock cycles
;
; RDPHF0: Phase F read clock cycle (TCONCS0.11 .. TCONCS0.12)
_RDPHF0     EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; WRPHF0: Phase F write clock cycle (TCONCS0.13 .. TCONCS0.14)
_WRPHF0     EQU    3    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS1 AREA ===========
;
; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
$SET (CONFIG_CS1 = 1)
;
; Definitions for Address Select register ADDRSEL1
; ================================================
;
_ADDR1      EQU 0x000000     ; Set CS1# Start Address (default 100000H)
;
_SIZE1      EQU 4096*KB      ; Set CS1# Size (default 1024*KB = 1*MB)
                             ; possible values for _SIZE1 are:
                             ;    4*KB            (gives RGSZ1 = 0)
                             ;    8*KB            (gives RGSZ1 = 1)
                             ;   16*KB            (gives RGSZ1 = 2)
                             ;   32*KB            (gives RGSZ1 = 3)
                             ;   64*KB            (gives RGSZ1 = 4)
                             ;  128*KB            (gives RGSZ1 = 5)
                             ;  256*KB            (gives RGSZ1 = 6)
                             ;  512*KB            (gives RGSZ1 = 7)
                             ; 1024*KB  or  1*MB  (gives RGSZ1 = 8)
                             ; 2048*KB  or  2*MB  (gives RGSZ1 = 9)
                             ; 4096*KB  or  4*MB  (gives RGSZ1 = 10)
                             ; 8192*KB  or  8*MB  (gives RGSZ1 = 11)
                             ;                    (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS1
; =======================================================
;
; ENCS1: Enable Chip Select (FCONCS1.0)
_ENCS1     EQU    1     ; 0 = Chip Select 0 disabled
                        ; 1 = Chip Select 0 enabled
;
; RDYEN1: Ready Enable (FCONCS1.1)
_RDYEN1    EQU    0     ; 0 = Access time controlled by TCONCS1.PHE1
                        ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
;
; RDYMOD1: Ready Mode (FCONCS1.2)
_RDYMOD1   EQU    1     ; 0 = Asynchronous READY
                        ; 1 = Synchronous READY
;
; BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
_BTYP1     EQU    2     ; 0 = 8 bit Demultiplexed bus
                        ; 1 = 8 bit Multiplexed bus
                        ; 2 = 16 bit Demultiplexed bus
                        ; 3 = 16 bit Multiplexed bus
;
;
; TCONCS1: Definitions for the Timing Configuration register 
; ==========================================================
;
; PHA1: Phase A clock cycle (TCONCS1.0 .. TCONCS1.1)
_PHA1       EQU    1    ; 0 = 0 clock cycles
                        ; : = : 
                        ; 3 = 3 clock cycles
;
; PHB1: Phase B clock cycle (TCONCS1.2)
_PHB1       EQU    0    ; 0 = 1 clock cycle
                        ; 1 = 2 clock cycles
;
; PHC1: Phase C clock cycle (TCONCS1.3 .. TCONCS1.4)
_PHC1       EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; PHD1: Phase D clock cycle (TCONCS1.5)
_PHD1       EQU    0    ; 0 = 0 clock cycles
                        ; 1 = 1 clock cycle
;
; PHE1: Phase E clock cycle (TCONCS1.6 .. TCONCS1.10)
_PHE1       EQU    2    ; 0 = 1 clock cycle
                        ; : = :
                        ; 31 = 32 clock cycles
;
; RDPHF1: Phase F read clock cycle (TCONCS1.11 .. TCONCS1.12)
_RDPHF1     EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; WRPHF1: Phase F write clock cycle (TCONCS1.13 .. TCONCS1.14)
_WRPHF1     EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS2 AREA ===========
;
; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
$SET (CONFIG_CS2 = 1)
;
; Definitions for Address Select register ADDRSEL2
; ================================================
;
_ADDR2      EQU 0x800000     ; Set CS2# Start Address (default 200000H)
;
_SIZE2      EQU 1*MB         ; Set CS2# Size (default 1024*KB = 1*MB)
                             ; possible values for _SIZE2 are:
                             ;    4*KB            (gives RGSZ1 = 0)
                             ;    8*KB            (gives RGSZ1 = 1)
                             ;   16*KB            (gives RGSZ1 = 2)
                             ;   32*KB            (gives RGSZ1 = 3)
                             ;   64*KB            (gives RGSZ1 = 4)
                             ;  128*KB            (gives RGSZ1 = 5)
                             ;  256*KB            (gives RGSZ1 = 6)
                             ;  512*KB            (gives RGSZ1 = 7)
                             ; 1024*KB  or  1*MB  (gives RGSZ1 = 8)
                             ; 2048*KB  or  2*MB  (gives RGSZ1 = 9)
                             ; 4096*KB  or  4*MB  (gives RGSZ1 = 10)
                             ; 8192*KB  or  8*MB  (gives RGSZ1 = 11)
                             ;                    (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS2
; =======================================================
;
; ENCS2: Enable Chip Select (FCONCS2.0)
_ENCS2     EQU    1     ; 0 = Chip Select 0 disabled
                        ; 1 = Chip Select 0 enabled
;
; RDYEN2: Ready Enable (FCONCS2.1)
_RDYEN2    EQU    0     ; 0 = Access time controlled by TCONCS2.PHE2
                        ; 1 = Access time cont. by TCONCS2.PHE2 and READY signal
;
; RDYMOD2: Ready Mode (FCONCS2.2)
_RDYMOD2   EQU    0     ; 0 = Asynchronous READY
                        ; 1 = Synchronous READY
;
; BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
_BTYP2     EQU    0     ; 0 = 8 bit Demultiplexed bus
                        ; 1 = 8 bit Multiplexed bus
                        ; 2 = 16 bit Demultiplexed bus
                        ; 3 = 16 bit Multiplexed bus
;
;
; TCONCS2: Definitions for the Timing Configuration register 
; ==========================================================
;
; PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1)
_PHA2       EQU    1    ; 0 = 0 clock cycles
                        ; : = : 
                        ; 3 = 3 clock cycles
;
; PHB2: Phase B clock cycle (TCONCS2.2)
_PHB2       EQU    0    ; 0 = 1 clock cycle
                        ; 1 = 2 clock cycles
;
; PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4)
_PHC2       EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; PHD2: Phase D clock cycle (TCONCS2.5)
_PHD2       EQU    0    ; 0 = 0 clock cycles
                        ; 1 = 1 clock cycle
;
; PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10)
_PHE2       EQU    2    ; 0 = 1 clock cycle
                        ; : = :
                        ; 31 = 32 clock cycles
;
; RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12)
_RDPHF2     EQU    1    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; WRPHF2: Phase F write clock cycle (TCONCS2.13 .. TCONCS2.14)
_WRPHF2     EQU    1    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS3 AREA ===========
;
; --- Set CONFIG_CS3 = 1 to initialize the ADDRSEL3/FCONCS3/TCONCS3 registers
$SET (CONFIG_CS3 = 1)
;
; Definitions for Address Select register ADDRSEL3
; ================================================
;
_ADDR3      EQU 0x900000     ; Set CS3# Start Address (default 300000H)
;
_SIZE3      EQU 1*MB         ; Set CS3# Size (default 1024*KB = 1*MB)
                             ; possible values for _SIZE3 are:
                             ;    4*KB            (gives RGSZ1 = 0)
                             ;    8*KB            (gives RGSZ1 = 1)
                             ;   16*KB            (gives RGSZ1 = 2)
                             ;   32*KB            (gives RGSZ1 = 3)
                             ;   64*KB            (gives RGSZ1 = 4)
                             ;  128*KB            (gives RGSZ1 = 5)
                             ;  256*KB            (gives RGSZ1 = 6)
                             ;  512*KB            (gives RGSZ1 = 7)
                             ; 1024*KB  or  1*MB  (gives RGSZ1 = 8)
                             ; 2048*KB  or  2*MB  (gives RGSZ1 = 9)
                             ; 4096*KB  or  4*MB  (gives RGSZ1 = 10)
                             ; 8192*KB  or  8*MB  (gives RGSZ1 = 11)
                             ;                    (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS3
; =======================================================
;
; ENCS3: Enable Chip Select (FCONCS3.0)
_ENCS3     EQU    1     ; 0 = Chip Select 0 disabled
                        ; 1 = Chip Select 0 enabled
;
; RDYEN3: Ready Enable (FCONCS3.1)
_RDYEN3    EQU    0     ; 0 = Access time controlled by TCONCS3.PHE3
                        ; 1 = Access time cont. by TCONCS3.PHE3 and READY signal
;
; RDYMOD3: Ready Mode (FCONCS3.2)
_RDYMOD3   EQU    0     ; 0 = Asynchronous READY
                        ; 1 = Synchronous READY
;
; BTYP3: Bus Type Selection (FCONCS3.4 .. FCONCS3.5)
_BTYP3     EQU    2     ; 0 = 8 bit Demultiplexed bus
                        ; 1 = 8 bit Multiplexed bus
                        ; 2 = 16 bit Demultiplexed bus
                        ; 3 = 16 bit Multiplexed bus
;
;
; TCONCS3: Definitions for the Timing Configuration register 
; ==========================================================
;
; PHA3: Phase A clock cycle (TCONCS3.0 .. TCONCS3.1)
_PHA3       EQU    3    ; 0 = 0 clock cycles
                        ; : = : 
                        ; 3 = 3 clock cycles
;
; PHB3: Phase B clock cycle (TCONCS3.2)
_PHB3       EQU    0    ; 0 = 1 clock cycle
                        ; 1 = 2 clock cycles
;
; PHC3: Phase C clock cycle (TCONCS3.3 .. TCONCS3.4)
_PHC3       EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; PHD3: Phase D clock cycle (TCONCS3.5)
_PHD3       EQU    0    ; 0 = 0 clock cycles
                        ; 1 = 1 clock cycle
;
; PHE3: Phase E clock cycle (TCONCS3.6 .. TCONCS3.10)
_PHE3       EQU    9    ; 0 = 1 clock cycle
                        ; : = :
                        ; 31 = 32 clock cycles
;
; RDPHF3: Phase F read clock cycle (TCONCS3.11 .. TCONCS3.12)
_RDPHF3     EQU    0    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
; WRPHF3: Phase F write clock cycle (TCONCS3.13 .. TCONCS3.14)
_WRPHF3     EQU    3    ; 0 = 0 clock cycles
                        ; : = :
                        ; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS4 AREA ===========
;
; --- Set CONFIG_CS4 = 1 to initialize the ADDRSEL4/FCONCS4/TCONCS4 registers
$SET (CONFIG_CS4 = 1)