📄 inst_v2.lst
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+1 679 ; 1 = Access time cont. by TCONCS2.PHE2 and READY signal
+1 680 ;
+1 681 ; RDYMOD2: Ready Mode (FCONCS2.2)
0000 +1 682 _RDYMOD2 EQU 0 ; 0 = Asynchronous READY
+1 683 ; 1 = Synchronous READY
+1 684 ;
+1 685 ; BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
0000 +1 686 _BTYP2 EQU 0 ; 0 = 8 bit Demultiplexed bus
+1 687 ; 1 = 8 bit Multiplexed bus
+1 688 ; 2 = 16 bit Demultiplexed bus
+1 689 ; 3 = 16 bit Multiplexed bus
+1 690 ;
+1 691 ;
+1 692 ; TCONCS2: Definitions for the Timing Configuration register
+1 693 ; ==========================================================
+1 694 ;
+1 695 ; PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1)
0001 +1 696 _PHA2 EQU 1 ; 0 = 0 clock cycles
+1 697 ; : = :
+1 698 ; 3 = 3 clock cycles
+1 699 ;
+1 700 ; PHB2: Phase B clock cycle (TCONCS2.2)
0000 +1 701 _PHB2 EQU 0 ; 0 = 1 clock cycle
+1 702 ; 1 = 2 clock cycles
+1 703 ;
+1 704 ; PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4)
0000 +1 705 _PHC2 EQU 0 ; 0 = 0 clock cycles
+1 706 ; : = :
+1 707 ; 3 = 3 clock cycles
+1 708 ;
+1 709 ; PHD2: Phase D clock cycle (TCONCS2.5)
0000 +1 710 _PHD2 EQU 0 ; 0 = 0 clock cycles
+1 711 ; 1 = 1 clock cycle
+1 712 ;
+1 713 ; PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10)
0002 +1 714 _PHE2 EQU 2 ; 0 = 1 clock cycle
+1 715 ; : = :
+1 716 ; 31 = 32 clock cycles
+1 717 ;
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 12
+1 718 ; RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12)
0001 +1 719 _RDPHF2 EQU 1 ; 0 = 0 clock cycles
+1 720 ; : = :
+1 721 ; 3 = 3 clock cycles
+1 722 ;
+1 723 ; WRPHF2: Phase F write clock cycle (TCONCS2.13 .. TCONCS2.14)
0001 +1 724 _WRPHF2 EQU 1 ; 0 = 0 clock cycles
+1 725 ; : = :
+1 726 ; 3 = 3 clock cycles
+1 727 ;
+1 728 ;
+1 729 ;
+1 730 ; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS3 AREA ===========
+1 731 ;
+1 732 ; --- Set CONFIG_CS3 = 1 to initialize the ADDRSEL3/FCONCS3/TCONCS3 registers
+1 733 $SET (CONFIG_CS3 = 1)
+1 734 ;
+1 735 ; Definitions for Address Select register ADDRSEL3
+1 736 ; ================================================
+1 737 ;
00900000 +1 738 _ADDR3 EQU 0x900000 ; Set CS3# Start Address (default 300000H)
+1 739 ;
00100000 +1 740 _SIZE3 EQU 1*MB ; Set CS3# Size (default 1024*KB = 1*MB)
+1 741 ; possible values for _SIZE3 are:
+1 742 ; 4*KB (gives RGSZ1 = 0)
+1 743 ; 8*KB (gives RGSZ1 = 1)
+1 744 ; 16*KB (gives RGSZ1 = 2)
+1 745 ; 32*KB (gives RGSZ1 = 3)
+1 746 ; 64*KB (gives RGSZ1 = 4)
+1 747 ; 128*KB (gives RGSZ1 = 5)
+1 748 ; 256*KB (gives RGSZ1 = 6)
+1 749 ; 512*KB (gives RGSZ1 = 7)
+1 750 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
+1 751 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
+1 752 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
+1 753 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
+1 754 ; (RGSZ1 = 12 .. 15 reserved)
+1 755 ;
+1 756 ; Definitions for Function Configuration Register FCONCS3
+1 757 ; =======================================================
+1 758 ;
+1 759 ; ENCS3: Enable Chip Select (FCONCS3.0)
0001 +1 760 _ENCS3 EQU 1 ; 0 = Chip Select 0 disabled
+1 761 ; 1 = Chip Select 0 enabled
+1 762 ;
+1 763 ; RDYEN3: Ready Enable (FCONCS3.1)
0000 +1 764 _RDYEN3 EQU 0 ; 0 = Access time controlled by TCONCS3.PHE3
+1 765 ; 1 = Access time cont. by TCONCS3.PHE3 and READY signal
+1 766 ;
+1 767 ; RDYMOD3: Ready Mode (FCONCS3.2)
0000 +1 768 _RDYMOD3 EQU 0 ; 0 = Asynchronous READY
+1 769 ; 1 = Synchronous READY
+1 770 ;
+1 771 ; BTYP3: Bus Type Selection (FCONCS3.4 .. FCONCS3.5)
0002 +1 772 _BTYP3 EQU 2 ; 0 = 8 bit Demultiplexed bus
+1 773 ; 1 = 8 bit Multiplexed bus
+1 774 ; 2 = 16 bit Demultiplexed bus
+1 775 ; 3 = 16 bit Multiplexed bus
+1 776 ;
+1 777 ;
+1 778 ; TCONCS3: Definitions for the Timing Configuration register
+1 779 ; ==========================================================
+1 780 ;
+1 781 ; PHA3: Phase A clock cycle (TCONCS3.0 .. TCONCS3.1)
0003 +1 782 _PHA3 EQU 3 ; 0 = 0 clock cycles
+1 783 ; : = :
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 13
+1 784 ; 3 = 3 clock cycles
+1 785 ;
+1 786 ; PHB3: Phase B clock cycle (TCONCS3.2)
0000 +1 787 _PHB3 EQU 0 ; 0 = 1 clock cycle
+1 788 ; 1 = 2 clock cycles
+1 789 ;
+1 790 ; PHC3: Phase C clock cycle (TCONCS3.3 .. TCONCS3.4)
0000 +1 791 _PHC3 EQU 0 ; 0 = 0 clock cycles
+1 792 ; : = :
+1 793 ; 3 = 3 clock cycles
+1 794 ;
+1 795 ; PHD3: Phase D clock cycle (TCONCS3.5)
0000 +1 796 _PHD3 EQU 0 ; 0 = 0 clock cycles
+1 797 ; 1 = 1 clock cycle
+1 798 ;
+1 799 ; PHE3: Phase E clock cycle (TCONCS3.6 .. TCONCS3.10)
0009 +1 800 _PHE3 EQU 9 ; 0 = 1 clock cycle
+1 801 ; : = :
+1 802 ; 31 = 32 clock cycles
+1 803 ;
+1 804 ; RDPHF3: Phase F read clock cycle (TCONCS3.11 .. TCONCS3.12)
0000 +1 805 _RDPHF3 EQU 0 ; 0 = 0 clock cycles
+1 806 ; : = :
+1 807 ; 3 = 3 clock cycles
+1 808 ;
+1 809 ; WRPHF3: Phase F write clock cycle (TCONCS3.13 .. TCONCS3.14)
0003 +1 810 _WRPHF3 EQU 3 ; 0 = 0 clock cycles
+1 811 ; : = :
+1 812 ; 3 = 3 clock cycles
+1 813 ;
+1 814 ;
+1 815 ;
+1 816 ; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS4 AREA ===========
+1 817 ;
+1 818 ; --- Set CONFIG_CS4 = 1 to initialize the ADDRSEL4/FCONCS4/TCONCS4 registers
+1 819 $SET (CONFIG_CS4 = 1)
+1 820 ;
+1 821 ; Definitions for Address Select register ADDRSEL4
+1 822 ; ================================================
+1 823 ;
00A00000 +1 824 _ADDR4 EQU 0xA00000 ; Set CS4# Start Address (default 400000H)
+1 825 ;
00100000 +1 826 _SIZE4 EQU 1*MB ; Set CS4# Size (default 1024*KB = 1*MB)
+1 827 ; possible values for _SIZE4 are:
+1 828 ; 4*KB (gives RGSZ1 = 0)
+1 829 ; 8*KB (gives RGSZ1 = 1)
+1 830 ; 16*KB (gives RGSZ1 = 2)
+1 831 ; 32*KB (gives RGSZ1 = 3)
+1 832 ; 64*KB (gives RGSZ1 = 4)
+1 833 ; 128*KB (gives RGSZ1 = 5)
+1 834 ; 256*KB (gives RGSZ1 = 6)
+1 835 ; 512*KB (gives RGSZ1 = 7)
+1 836 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
+1 837 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
+1 838 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
+1 839 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
+1 840 ; (RGSZ1 = 12 .. 15 reserved)
+1 841 ;
+1 842 ; Definitions for Function Configuration Register FCONCS4
+1 843 ; =======================================================
+1 844 ;
+1 845 ; ENCS4: Enable Chip Select (FCONCS4.0)
0001 +1 846 _ENCS4 EQU 1 ; 0 = Chip Select 0 disabled
+1 847 ; 1 = Chip Select 0 enabled
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