📄 inst_v2.lst
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+1 508 ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
+1 509 ;
+1 510 ; RDYMOD0: Ready Mode (FCONCS0.2)
0000 +1 511 _RDYMOD0 EQU 0 ; 0 = Asynchronous READY
+1 512 ; 1 = Synchronous READY
+1 513 ;
+1 514 ; BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
0002 +1 515 _BTYP0 EQU 2 ; 0 = 8 bit Demultiplexed bus
+1 516 ; 1 = 8 bit Multiplexed bus
+1 517 ; 2 = 16 bit Demultiplexed bus
+1 518 ; 3 = 16 bit Multiplexed bus
+1 519 ;
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 9
+1 520 ;
+1 521 ; TCONCS0: Definitions for the Timing Configuration register
+1 522 ; ==========================================================
+1 523 ;
+1 524 ; PHA0: Phase A clock cycle (TCONCS0.0 .. TCONCS0.1)
0001 +1 525 _PHA0 EQU 1 ; 0 = 0 clock cycles
+1 526 ; : = :
+1 527 ; 3 = 3 clock cycles
+1 528 ;
+1 529 ; PHB0: Phase B clock cycle (TCONCS0.2)
0000 +1 530 _PHB0 EQU 0 ; 0 = 1 clock cycle
+1 531 ; 1 = 2 clock cycles
+1 532 ;
+1 533 ; PHC0: Phase C clock cycle (TCONCS0.3 .. TCONCS0.4)
0001 +1 534 _PHC0 EQU 1 ; 0 = 0 clock cycles
+1 535 ; : = :
+1 536 ; 3 = 3 clock cycles
+1 537 ;
+1 538 ; PHD0: Phase D clock cycle (TCONCS0.5)
0000 +1 539 _PHD0 EQU 0 ; 0 = 0 clock cycles
+1 540 ; 1 = 1 clock cycle
+1 541 ;
+1 542 ; PHE0: Phase E clock cycle (TCONCS0.6 .. TCONCS0.10)
0003 +1 543 _PHE0 EQU 3 ; 0 = 1 clock cycle
+1 544 ; : = :
+1 545 ; 31 = 32 clock cycles
+1 546 ;
+1 547 ; RDPHF0: Phase F read clock cycle (TCONCS0.11 .. TCONCS0.12)
0000 +1 548 _RDPHF0 EQU 0 ; 0 = 0 clock cycles
+1 549 ; : = :
+1 550 ; 3 = 3 clock cycles
+1 551 ;
+1 552 ; WRPHF0: Phase F write clock cycle (TCONCS0.13 .. TCONCS0.14)
0003 +1 553 _WRPHF0 EQU 3 ; 0 = 0 clock cycles
+1 554 ; : = :
+1 555 ; 3 = 3 clock cycles
+1 556 ;
+1 557 ;
+1 558 ; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS1 AREA ===========
+1 559 ;
+1 560 ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
+1 561 $SET (CONFIG_CS1 = 1)
+1 562 ;
+1 563 ; Definitions for Address Select register ADDRSEL1
+1 564 ; ================================================
+1 565 ;
0000 +1 566 _ADDR1 EQU 0x000000 ; Set CS1# Start Address (default 100000H)
+1 567 ;
00400000 +1 568 _SIZE1 EQU 4096*KB ; Set CS1# Size (default 1024*KB = 1*MB)
+1 569 ; possible values for _SIZE1 are:
+1 570 ; 4*KB (gives RGSZ1 = 0)
+1 571 ; 8*KB (gives RGSZ1 = 1)
+1 572 ; 16*KB (gives RGSZ1 = 2)
+1 573 ; 32*KB (gives RGSZ1 = 3)
+1 574 ; 64*KB (gives RGSZ1 = 4)
+1 575 ; 128*KB (gives RGSZ1 = 5)
+1 576 ; 256*KB (gives RGSZ1 = 6)
+1 577 ; 512*KB (gives RGSZ1 = 7)
+1 578 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
+1 579 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
+1 580 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
+1 581 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
+1 582 ; (RGSZ1 = 12 .. 15 reserved)
+1 583 ;
+1 584 ; Definitions for Function Configuration Register FCONCS1
+1 585 ; =======================================================
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 10
+1 586 ;
+1 587 ; ENCS1: Enable Chip Select (FCONCS1.0)
0001 +1 588 _ENCS1 EQU 1 ; 0 = Chip Select 0 disabled
+1 589 ; 1 = Chip Select 0 enabled
+1 590 ;
+1 591 ; RDYEN1: Ready Enable (FCONCS1.1)
0000 +1 592 _RDYEN1 EQU 0 ; 0 = Access time controlled by TCONCS1.PHE1
+1 593 ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
+1 594 ;
+1 595 ; RDYMOD1: Ready Mode (FCONCS1.2)
0001 +1 596 _RDYMOD1 EQU 1 ; 0 = Asynchronous READY
+1 597 ; 1 = Synchronous READY
+1 598 ;
+1 599 ; BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
0002 +1 600 _BTYP1 EQU 2 ; 0 = 8 bit Demultiplexed bus
+1 601 ; 1 = 8 bit Multiplexed bus
+1 602 ; 2 = 16 bit Demultiplexed bus
+1 603 ; 3 = 16 bit Multiplexed bus
+1 604 ;
+1 605 ;
+1 606 ; TCONCS1: Definitions for the Timing Configuration register
+1 607 ; ==========================================================
+1 608 ;
+1 609 ; PHA1: Phase A clock cycle (TCONCS1.0 .. TCONCS1.1)
0001 +1 610 _PHA1 EQU 1 ; 0 = 0 clock cycles
+1 611 ; : = :
+1 612 ; 3 = 3 clock cycles
+1 613 ;
+1 614 ; PHB1: Phase B clock cycle (TCONCS1.2)
0000 +1 615 _PHB1 EQU 0 ; 0 = 1 clock cycle
+1 616 ; 1 = 2 clock cycles
+1 617 ;
+1 618 ; PHC1: Phase C clock cycle (TCONCS1.3 .. TCONCS1.4)
0000 +1 619 _PHC1 EQU 0 ; 0 = 0 clock cycles
+1 620 ; : = :
+1 621 ; 3 = 3 clock cycles
+1 622 ;
+1 623 ; PHD1: Phase D clock cycle (TCONCS1.5)
0000 +1 624 _PHD1 EQU 0 ; 0 = 0 clock cycles
+1 625 ; 1 = 1 clock cycle
+1 626 ;
+1 627 ; PHE1: Phase E clock cycle (TCONCS1.6 .. TCONCS1.10)
0002 +1 628 _PHE1 EQU 2 ; 0 = 1 clock cycle
+1 629 ; : = :
+1 630 ; 31 = 32 clock cycles
+1 631 ;
+1 632 ; RDPHF1: Phase F read clock cycle (TCONCS1.11 .. TCONCS1.12)
0000 +1 633 _RDPHF1 EQU 0 ; 0 = 0 clock cycles
+1 634 ; : = :
+1 635 ; 3 = 3 clock cycles
+1 636 ;
+1 637 ; WRPHF1: Phase F write clock cycle (TCONCS1.13 .. TCONCS1.14)
0000 +1 638 _WRPHF1 EQU 0 ; 0 = 0 clock cycles
+1 639 ; : = :
+1 640 ; 3 = 3 clock cycles
+1 641 ;
+1 642 ;
+1 643 ;
+1 644 ; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS2 AREA ===========
+1 645 ;
+1 646 ; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
+1 647 $SET (CONFIG_CS2 = 1)
+1 648 ;
+1 649 ; Definitions for Address Select register ADDRSEL2
+1 650 ; ================================================
+1 651 ;
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 11
00800000 +1 652 _ADDR2 EQU 0x800000 ; Set CS2# Start Address (default 200000H)
+1 653 ;
00100000 +1 654 _SIZE2 EQU 1*MB ; Set CS2# Size (default 1024*KB = 1*MB)
+1 655 ; possible values for _SIZE2 are:
+1 656 ; 4*KB (gives RGSZ1 = 0)
+1 657 ; 8*KB (gives RGSZ1 = 1)
+1 658 ; 16*KB (gives RGSZ1 = 2)
+1 659 ; 32*KB (gives RGSZ1 = 3)
+1 660 ; 64*KB (gives RGSZ1 = 4)
+1 661 ; 128*KB (gives RGSZ1 = 5)
+1 662 ; 256*KB (gives RGSZ1 = 6)
+1 663 ; 512*KB (gives RGSZ1 = 7)
+1 664 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
+1 665 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
+1 666 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
+1 667 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
+1 668 ; (RGSZ1 = 12 .. 15 reserved)
+1 669 ;
+1 670 ; Definitions for Function Configuration Register FCONCS2
+1 671 ; =======================================================
+1 672 ;
+1 673 ; ENCS2: Enable Chip Select (FCONCS2.0)
0001 +1 674 _ENCS2 EQU 1 ; 0 = Chip Select 0 disabled
+1 675 ; 1 = Chip Select 0 enabled
+1 676 ;
+1 677 ; RDYEN2: Ready Enable (FCONCS2.1)
0000 +1 678 _RDYEN2 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE2
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