📄 inst_v2.lst
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+1 335 ; 5 = 64 t_CPU clocks
+1 336 ; 6 = 128 t_CPU clocks
+1 337 ; 7 = 256 t_CPU clocks
+1 338 ;
+1 339 ; RORMV: RSTOUT# Remove Control (RSTCON.4)
0000 +1 340 _RORMV EQU 0 ; 0 = RSTOUT delievers RSTOUT# signal
+1 341 ; 1 = RSTOUT pin operates as GPIO
+1 342 ;
+1 343 ; ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
0000 +1 344 _ROCOFF EQU 0 ; 0 = RSTOUT is deactivated by user software
+1 345 ; 1 = RSTOUT is deactiveted at end of reset
+1 346 ;
+1 347 ; ROCON: RSTOUT# Control Switch Off (RSTCON.6)
0000 +1 348 _ROCON EQU 0 ; 0 = RSTOUT is activated upon any reset
+1 349 ; 1 = RSTOUT is only activated upon a hardware reset
+1 350 ;
+1 351 ; RODIS: RSTOUT# Disable Control (RSTCON.7)
0000 +1 352 _RODIS EQU 0 ; 0 = RSTOUT is controlled by other mechanism
+1 353 ; 1 = RSTOUT is deactivated
+1 354 ;
+1 355 ;
+1 356 ;
+1 357 ; Definitions for PLL Control Register PLLCON
+1 358 ; ===========================================
+1 359 ;
+1 360 ; INIT_PLLCON: Init PLLCON register
+1 361 ; --- Set INIT_PLLCON = 1 to initilize the PLLCON register
+1 $IF (NO_EA)
+1 $SET (INIT_PLLCON = 1)
+1 364 $ELSE
+1 365 $SET (INIT_PLLCON = 0)
+1 366 $ENDIF
+1 367 ;
+1 368 ; PLLODIV: PLL Output Devider (PLLCON.0 .. PLLCON.3)
0004 +1 369 _PLLODIV EQU 4 ; 0 .. 14 Fpll = Fvco / (PLLODIV+1)
+1 370 ; 15 = reserved
+1 371 ;
+1 372 ; PLLIDIV: PLL Input Devider (PLLCON.4 .. PLLCON.5)
0000 +1 373 _PLLIDIV EQU 0 ; 0 .. 3 Fin = Fosc / (PLLIDIV+1)
+1 374 ;
+1 375 ; PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
0002 +1 376 _PLLVB EQU 2 ; ValueVCO output frequency Base frequency
+1 377 ; 0 = 100...150 MHz 20...80 MHz
+1 378 ; 1 = 150...200 MHz 40...130 MHz
+1 379 ; 2 = 200...250 MHz [def.] 60...180 MHz
+1 380 ; 3 = (250...300 MHz) Reserved
+1 381 ;
+1 382 ; PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12)
0018 +1 383 _PLLMUL EQU 24 ; 7 .. 31 Fvco = Fin * (PLLMUL+1)
+1 384 ; 0 .. 6 = reserved
+1 385 ;
+1 386 ; PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
0003 +1 387 _PLLCTRL EQU 3 ; 0 = Bypass PLL clock mult., the VCO is off
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 7
+1 388 ; 1 = Bypass PLL clock mult., the VCO is running
+1 389 ; 2 = VCO clock used, input clock switched off
+1 390 ; 3 = VCO clock used, input clock connected
+1 391 ;
+1 392 ; PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
0000 +1 393 _PLLWRI EQU 0 ; 0 = Register PLLCON may be written
+1 394 ; 1 = Write cycles to register PLLCON are ignored
+1 395 ;
+1 396 ;
+1 397 ; Definitions for Frequency Output Signal FOCON
+1 398 ; =============================================
+1 399 ;
+1 400 ; INIT_FOCON: Init FOCON register
+1 401 ; --- Set INIT_FOCON = 1 to initilize the FOCON register
+1 402 $SET (INIT_FOCON = 1)
+1 403 ;
+1 404 ; CLKEN: CLKOUT Enable (FOCON.7)
0001 +1 405 _CLKEN EQU 1 ; 0 = P3.15 is IO pin when _FOUT is 0
+1 406 ; 1 = P3.15 outputs signal CLKOUT
+1 407 ;
+1 408 ; FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13)
0000 +1 409 _FORV EQU 0 ; is copied to FOCNT upon each underflow of FOCNT
+1 410 ;
+1 411 ; FOSS: Frequency Output Signal Select (FOCON.14)
0000 +1 412 _FOSS EQU 0 ; 0 = Output of the toggle latch; 0.5 duty cycle
+1 413 ; 1 = Output of reload counter; duty cycle depends on FORV
+1 414 ;
+1 415 ; FOEN: Frequency Output Enable (FOCON.15)
0001 +1 416 _FOEN EQU 1 ; 0 = P3.15 is IO pin when _CLKEN is 0
+1 417 ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
+1 418 ;
+1 419 ;
+1 420 ; ============= CONFIGURE EXTERNAL BUS (EBC) BEHAVIOUR =====================
+1 421 ;
+1 422 ; --- Set CONFIG_EBC = 1 to initialize the EBCMOD0/EBCMOD1 registers
+1 423 $SET (CONFIG_EBC = 1) ; 0 = EBCMOD0/EBCMOD1 are set during reset according the
+1 424 ; of configuration bus (typical Port0) values.
+1 425 ; 1 = the following external bus configuration values
+1 426 ; are written to EBCMOD and BUSACT0
+1 427 ;
+1 428 ; Definitions for EBC Mode 0 register EBCMOD0
+1 429 ; ===========================================
+1 430 ;
+1 431 ; SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3)
0004 +1 432 _SAPEN EQU 4 ; 0 = No segment address pins enabled
+1 433 ; 1 = One (A16) segment address pin enabled
+1 434 ; : = :
+1 435 ; 8 = Eight (A16 .. A23) address pins enabled
+1 436 ; 9 - 15 = reserved
+1 437 ;
+1 438 ; CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7)
0005 +1 439 _CSPEN EQU 5 ; 0 = No CS pins enabled
+1 440 ; 1 = One CS (CS0) pin enabled
+1 441 ; : = :
+1 442 ; 8 = Eight CS (CS0 .. CS7) pins enabled
+1 443 ; 9 - 15 = reserved
+1 444 ; Note: the number of available CS pins depends on the chip used
+1 445 ;
+1 446 ; ARBEN: Bus Arbitration Pins Enabled (EBCMOD0.8)
0000 +1 447 _ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
+1 448 ; 1 = HOLD, HLDA and BREQ pins act normally
+1 449 ;
+1 450 ; SLAVE: SLAVE mode enable (EBCMOD0.9)
0000 +1 451 _SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode
+1 452 ; 1 = Bus arbiter acts in slave mode
+1 453 ;
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 8
+1 454 ; EBCDIS: EBC pins disable (EBCMOD0.10)
0000 +1 455 _EBCDIS EQU 0 ; 0 = EBC is using the pins for external bus
+1 456 ; 1 = EBC off (pins to be used as GPIO if implemented)
+1 457 ;
+1 458 ; WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
0001 +1 459 _WRCFG EQU 1 ; 0 = Pins act as WR and BHE
+1 460 ; 1 = Pins act as WRL and WRH
+1 461 ;
+1 462 ; BYTDIS: BHE pin disable (EBCMOD0.12)
0000 +1 463 _BYTDIS EQU 0 ; 0 = BHE enabled
+1 464 ; 1 = BHE disabled (GPIO function if implemented)
+1 465 ;
+1 466 ; ALEDIS: ALE pin disable (EBCMOD0.13)
0000 +1 467 _ALEDIS EQU 0 ; 0 = ALE pin enabled
+1 468 ; 1 = ALE pin disabled (GPIO function if implemented)
+1 469 ;
+1 470 ; RDYDIS: READY pin disable (EBCMOD0.14)
0001 +1 471 _RDYDIS EQU 1 ; 0 = READY enabled
+1 472 ; 1 = READY disabled (GPIO function if implemented)
+1 473 ;
+1 474 ; RDYPOL: READY pin polarity (EBCMOD0.15)
0000 +1 475 _RDYPOL EQU 0 ; 0 = READY pin is active low
+1 476 ; 1 = READY pin is active high
+1 477 ;
+1 478 ;
+1 479 ;
+1 480 ; Definitions for EBC Mode 1 register EBCMOD1
+1 481 ; ===========================================
+1 482 ;
+1 483 ; APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD0.4)
0000 +1 484 _APDIS EQU 0 ; 0 = Address port PORT1 used as address bus
+1 485 ; 1 - 30 = reserved
+1 486 ; 31 = Address bus disabled (PORT1 used as GPIO)
+1 487 ;
+1 488 ; DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
0000 +1 489 _DHPDIS EQU 0 ; 0 = Data bus pins 15-8 of PORT0 enabled
+1 490 ; 1 = Data bus pins 15-8 disabled (used as GPIO)
+1 491 ;
+1 492 ;
+1 493 ;
+1 494 ; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS0 AREA ===========
+1 495 ;
+1 496 ; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
+1 497 $SET (CONFIG_CS0 = 1)
+1 498 ;
+1 499 ; Definitions for Function Configuration Register FCONCS0
+1 500 ; =======================================================
+1 501 ;
+1 502 ; ENCS0: Enable Chip Select (FCONCS0.0)
0001 +1 503 _ENCS0 EQU 1 ; 0 = Chip Select 0 disabled
+1 504 ; 1 = Chip Select 0 enabled
+1 505 ;
+1 506 ; RDYEN0: Ready Enable (FCONCS0.1)
0000 +1 507 _RDYEN0 EQU 0 ; 0 = Access time controlled by TCONCS0.PHE0
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