📄 inst_v2.lst
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+1 164 ;
+1 165 ; CPU_CLOCK: Defines the internal CPU Clock frequency
+1 166 ; Notes: The internal Clock might be different from the XTAL frequency, due
+1 167 ; to on-chip PLL. This setting is not relevant for BOOTSTRAP Mode.
02625A00 +1 168 CPU_CLOCK EQU 40000000 ; default clock for most chips is 20MHz
+1 169 ;
+1 170 ;------------------------------------------------------------------------------
+1 171 ; Definitions for Cpu Configuration Register CPUCON1
+1 172 ; ==================================================
+1 173 ;
+1 174 ; ZCJ: Zero Cycle Jump Function (CPUCON1.0):
0000 +1 175 _ZCJ EQU 0 ; 0 = Disable Zero Cycle Jump Function
+1 176 ; 1 = Enable Zero Cycle Jump Function
+1 177 ;
+1 178 ; BP: Branch Prediction Unit (CPUCON1.1):
0000 +1 179 _BP EQU 0 ; 0 = Disable Branch Prediction Unit
+1 180 ; 1 = Enable Branch Prediction Unit
+1 181 ;
+1 182 ; INTSCXT: Interruptability of Switch Context Instruction (CPUCON1.2):
0000 +1 183 _INTSCXT EQU 0 ; 0 = Disable Interruption of SCXT instruction
+1 184 ; 1 = Enable Interruption of SCXT instruction
+1 185 ;
+1 186 ; SGTDIS: Disable Segmentation Control (CPUCON1.3):
+1 $IF TINY
+1 _SGTDIS EQU 1 ; disable segmented mode for TINY model
+1 189 $ELSE
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 4
0000 +1 190 _SGTDIS EQU 0 ; enable segmented mode (Reset Value)
+1 191 $ENDIF
+1 192 ;
+1 193 ; WDTCTL: Watchdog Timer Control (CPUCON1.4):
0000 +1 194 _WDTCTL EQU 0 ; 0 = DISWDT executable until end of EINIT
+1 195 ; 1 = DISWDT/ENWDT always executable
+1 196 ;
+1 197 ; VECSC: Vector Table Scaling Factor (CPUCON1.5 .. CPUCON1.6)
0000 +1 198 _VECSC EQU 0 ; 0 = Space between two vectors is 2 words
+1 199 ; 1 = Space between two vectors is 4 words
+1 200 ; 2 = Space between two vectors is 8 words
+1 201 ; 3 = Space between two vectors is 16 words
+1 202 ;
+1 203 ;
+1 204 ; Definitions for CPU Configuration Register CPUCON2
+1 205 ; ==================================================
+1 206 ;
+1 207 ; INIT_CPUCON2: Init CPUCON2 register
+1 208 ; --- Set INIT_CPUCON2 = 1 to initilize the SYSCON1 register
+1 209 $SET (INIT_CPUCON2 = 0) ; default: do not initilize CPUCON2
+1 210 ;
+1 211 ; SL: Short Loop Mode (CPUCON2.0)
0001 +1 212 _SL EQU 1 ; 0 = Short Loop mode disabled
+1 213 ; 1 = Short Loop mode enabled
+1 214 ;
+1 215 ; FASTPEC: Fast Pec Event Injection (CPUCON2.1)
0001 +1 216 _FASTPEC EQU 1 ; 0 = Direct Injection of PEC Events disabled
+1 217 ; 1 = Direct Injection of PEC Events enabled
+1 218 ;
+1 219 ; FASTBL: Fast Block Transfer Injection (CPUCON2.2)
0000 +1 220 _FASTBL EQU 0 ; 0 = Direct Injection for Block Transfers disabled
+1 221 ; 1 = Direct Injection for Block Transfers enabled
+1 222 ;
+1 223 ; RETST: Return Stack (CPUCON2.3)
0001 +1 224 _RETST EQU 1 ; 0 = Return Stack disabled
+1 225 ; 1 = Return Stack enabled
+1 226 ;
+1 227 ; OVRUN: Pipeline Bubble Overrun (CPUCON2.4)
0001 +1 228 _OVRUN EQU 1 ; 0 = Overrun of Pipeline Bubbles not allowed
+1 229 ; 1 = Overrun of Pipeline Bubbles allowed
+1 230 ;
+1 231 ; ZSC: Zero Cycle Jump Cache (CPUCON2.5)
0001 +1 232 _ZSC EQU 1 ; 0 = Zero Cycle Jump Cache disabled
+1 233 ; 1 = Zero Cycle Jump Cache enabled
+1 234 ;
+1 235 ; STEN: Stall Instruction (CPUCON2.6)
0000 +1 236 _STEN EQU 0 ; 0 = Stall instruction disabled
+1 237 ; 1 = Stall instruction enabled
+1 238 ;
+1 239 ; EIOIAEN: Early IO Injection Acknowledge
0001 +1 240 _EIOIAEN EQU 1 ; 0 = Injection ack. by destructive read not guaranteed
+1 241 ; ; 1 = Injection ack. by destructive read guaranteed
+1 242 ;
+1 243 ; BYPF: Fetch Bypass Control (CPUCON2.8)
0001 +1 244 _BYPF EQU 1 ; 0 = Bypass Path from Fetch to Decode disabled
+1 245 ; 1 = Bypass Path from Fetch to Decode enabled
+1 246 ;
+1 247 ; BYPPF: Prefecth Bypass Control (CPUCON2.9)
0001 +1 248 _BYPPF EQU 1 ; 0 = Bypass Path from Prefetch to Decode disabled
+1 249 ; 1 = Bypass Path from Prefetch to Decode enabled
+1 250 ;
+1 251 ; FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
0003 +1 252 _FIFOFED EQU 3 ; 0 = FIFO disabled
+1 253 ; 1 = FIFO filled with up to 1 instruction per cycle
+1 254 ; 2 = FIFO filled with up to 2 instructions per cycle
+1 255 ; 3 = FIFO filled with up to 3 instructions per cycle
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 5
+1 256 ;
+1 257 ; FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15)
0008 +1 258 _FIFODEPTH EQU 8 ; 0 = No FIFO entries (No FIFO)
+1 259 ; 1 = 1 FIFO entry
+1 260 ; ...
+1 261 ; 8 = 8 FIFO entries
+1 262 ; 9 - 15 = reserved
+1 263 ;
+1 264 ;
+1 265 ; Definitions for System Configuration Register SYSCON1
+1 266 ; =====================================================
+1 267 ;
+1 268 ; INIT_SYSCON1: Init SYSCON1 register
+1 269 ; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON3 register
+1 270 $SET (INIT_SYSCON1 = 1)
+1 271 ;
+1 272 ; SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
0000 +1 273 _SLEEPCON EQU 0 ; 0 = Normal IDLE mode entered upone IDLE instruction
+1 274 ; 1 = SLEEP mode entered upone IDLE instruction
+1 275 ; 2 - 3 = reserved
+1 276 ;
+1 277 ; PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
0000 +1 278 _PDCFG EQU 0 ; 0 = Port drivers are always ON (default)
+1 279 ; 1 = Port drivers are off in IDLE or Sleep mode
+1 280 ; 2 = Port drivers are off in Powerdown mode
+1 281 ; 3 = reserved
+1 282 ;
+1 283 ; PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
0000 +1 284 _PFCFG EQU 0 ; 0 = Program Flash is always ON (default)
+1 285 ; 1 = Program Flash is off in IDLE or Sleep mode
+1 286 ; 2 - 3 = reserved
+1 287 ;
+1 288 ; CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
0000 +1 289 _CPSYS EQU 0 ; 0 = clock signal for CPU is PLL frequency
+1 290 ; 1 = clock signal for CPU is PLL frequency / 2
+1 291 ; 2 - 7 = reserved
+1 292 ;
+1 293 ;
+1 294 ; Definitions for System Configuration Register SYSCON3
+1 295 ; =====================================================
+1 296 ;
+1 297 ; INIT_SYSCON3: Init SYSCON3 register
+1 298 ; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
+1 299 $SET (INIT_SYSCON3 = 1)
+1 300 ;
+1 301 ; SYSCON3: Power Management (disable on-chip peripherals)
+1 302 ;
0000 +1 303 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0)
0000 +1 304 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1)
0000 +1 305 SSC0DIS EQU 0 ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2)
0000 +1 306 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3)
+1 307 ; reserved (SYSCON3.4)
0000 +1 308 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
0000 +1 309 CC1DIS EQU 0 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6)
0000 +1 310 CC2DIS EQU 0 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7)
0000 +1 311 CC6DIS EQU 0 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8)
+1 312 ; reserved (SYSCON3.9)
0000 +1 313 ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10)
0000 +1 314 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11)
0000 +1 315 SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module (SYSCON3.12)
0000 +1 316 CANDIS EQU 0 ; 1 = disable on-chip CAN Module (SYSCON3.13)
+1 317 ; reserved (SYSCON3.14)
0000 +1 318 SSC1DIS EQU 0 ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15)
+1 319 ;
+1 320 ;
+1 321 ;
A166 MACRO ASSEMBLER Configuration for MONITOR (C) 2001 KEIL 07/09/2003 18:04:44 PAGE 6
+1 322 ; Definitions for Reset Configuration Register RSTCON
+1 323 ; ===================================================
+1 324 ;
+1 325 ; INIT_RSTCON: Init RSTCON register
+1 326 ; --- Set INIT_RSTCON = 1 to initilize the RSTCON register
+1 327 $SET (INIT_RSTCON = 0)
+1 328 ;
+1 329 ; RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
0000 +1 330 _RSTLEN EQU 0 ; 0 = 2 t_CPU clocks (default)
+1 331 ; 1 = 4 t_CPU clocks
+1 332 ; 2 = 8 t_CPU clocks
+1 333 ; 3 = 16 t_CPU clocks
+1 334 ; 4 = 32 t_CPU clocks
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