📄 inst_v2.a66
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$ENDIF
$IF (CONFIG_CS3)
; Set TCONCS3 register
_TCS3 SET (_PHD3<<5) OR (_PHC3<<3) OR (_PHB3<<2) OR (_PHA3)
_TCS3 SET _TCS3 OR (_WRPHF3<<13) OR (_RDPHF3<<11) OR (_PHE3<<6)
MOV R0,#_TCS3
MOV TCONCS3,R0
; Set ADDRSEL3 register
CALC_ADDRSEL _ADDRSEL3, _ADDR3, _SIZE3
MOV R0,#_ADDRSEL3
MOV ADDRSEL3,R0
; Set FCONCS3 register
_FCS3 SET (_BTYP3<<4) OR (_RDYMOD3<<2) OR (_RDYEN3<<1) OR (_ENCS3)
MOV R0,#_FCS3
MOV FCONCS3,R0
$ENDIF
$IF (CONFIG_CS4)
; Set TCONCS4 register
_TCS4 SET (_PHD4<<5) OR (_PHC4<<3) OR (_PHB4<<2) OR (_PHA4)
_TCS4 SET _TCS4 OR (_WRPHF4<<13) OR (_RDPHF4<<11) OR (_PHE4<<6)
MOV R0,#_TCS4
MOV TCONCS4,R0
; Set ADDRSEL4 register
CALC_ADDRSEL _ADDRSEL4, _ADDR4, _SIZE4
MOV R0,#_ADDRSEL4
MOV ADDRSEL4,R0
; Set FCONCS4 register
_FCS4 SET (_BTYP4<<4) OR (_RDYMOD4<<2) OR (_RDYEN4<<1) OR (_ENCS4)
MOV R0,#_FCS4
MOV FCONCS4,R0
$ENDIF
$IF (CONFIG_CS5)
; Set TCONCS5 register
_TCS5 SET (_PHD5<<5) OR (_PHC5<<3) OR (_PHB5<<2) OR (_PHA5)
_TCS5 SET _TCS5 OR (_WRPHF5<<13) OR (_RDPHF5<<11) OR (_PHE5<<6)
MOV R0,#_TCS5
MOV TCONCS5,R0
; Set ADDRSEL5 register
CALC_ADDRSEL _ADDRSEL5, _ADDR5, _SIZE5
MOV R0,#_ADDRSEL5
MOV ADDRSEL5,R0
; Set FCONCS5 register
_FCS5 SET (_BTYP5<<4) OR (_RDYMOD5<<2) OR (_RDYEN5<<1) OR (_ENCS5)
MOV R0,#_FCS5
MOV FCONCS5,R0
$ENDIF
$IF (CONFIG_CS6)
; Set TCONCS6 register
_TCS6 SET (_PHD6<<5) OR (_PHC6<<3) OR (_PHB6<<2) OR (_PHA6)
_TCS6 SET _TCS6 OR (_WRPHF6<<13) OR (_RDPHF6<<11) OR (_PHE6<<6)
MOV R0,#_TCS6
MOV TCONCS6,R0
; Set ADDRSEL6 register
CALC_ADDRSEL _ADDRSEL6, _ADDR6, _SIZE6
MOV R0,#_ADDRSEL6
MOV ADDRSEL6,R0
; Set FCONCS6 register
_FCS6 SET (_BTYP6<<4) OR (_RDYMOD6<<2) OR (_RDYEN6<<1) OR (_ENCS6)
MOV R0,#_FCS6
MOV FCONCS6,R0
$ENDIF
$IF (CONFIG_CS7)
; Set TCONCS7 register
_TCS7 SET (_PHD7<<5) OR (_PHC7<<3) OR (_PHB7<<2) OR (_PHA7)
_TCS7 SET _TCS7 OR (_WRPHF7<<13) OR (_RDPHF7<<11) OR (_PHE7<<6)
MOV R0,#_TCS7
MOV TCONCS7,R0
; Set ADDRSEL7 register
CALC_ADDRSEL _ADDRSEL7, _ADDR7, _SIZE7
MOV R0,#_ADDRSEL7
MOV ADDRSEL7,R0
; Set FCONCS7 register
_FCS7 SET (_BTYP7<<4) OR (_RDYMOD7<<2) OR (_RDYEN7<<1) OR (_ENCS7)
MOV R0,#_FCS7
MOV FCONCS7,R0
$ENDIF
$IF (INIT_RSTCON = 1) ; Set RSTCON register
_RSTCON SET (_ROCOFF<<5) OR (_RORMV<<4) OR (_RSTLEN)
_RSTCON SET _RSTCON OR (_RODIS<<7) OR (_ROCON<<6)
MOV R0,#_RSTCON
MOV RSTCON,R0
$ENDIF
$IF (INIT_PLLCON = 1) ; Set PLLCON register
_PLLCON SET (_PLLVB<<6) OR (_PLLIDIV<<4) OR (_PLLODIV)
_PLLCON SET _PLLCON OR (_PLLWRI<<15) OR (_PLLCTRL<<13) OR (_PLLMUL<<8)
EXTR #01H ; Extended SFR access
MOV PLLCON,#_PLLCON
$ENDIF
$IF (INIT_FOCON = 1) ; Set FOCON register
_FOCON SET (_CLKEN<<7) OR (_FORV<<8) OR (_FOSS<<14) OR (_FOEN<<15)
MOV FOCON,#_FOCON
$ENDIF
;
; Set VECSEG register
MOV VECSEG,#INT_ADR_SEG
; Kein EINIT im Monitor, damit das Anwenderprogramm noch 鋘dern kann
; EINIT
$ENDIF
$IF SERIAL0
;********************************************************************
;* Initialization of Serial Interface 0 *
;********************************************************************
$IF NOT (BOOTSTRAP) ; skip initialization when using bootstrap loader
BSET P3.10 ; SET PORT 3.10 OUTPUT LATCH (TXD)
NOP
BSET DP3.10 ; SET PORT 3.10 DIRECTION CONTROL (TXD OUTPUT)
NOP
BCLR DP3.11 ; RESET PORT 3.11 DIRECTION CONTROL (RXD INPUT)
MOVB S0TIC,#080H ; SET TRANSMIT INTERRUPT FLAG
MOVB S0RIC,#000H ; DELETE RECEIVE INTERRUPT FLAG
IF (BAUDRATE = 0)
; Auto adjust Baudrate
WStrtB:
JB P3.11,WStrtB ; wait for start bit at RXD0
BSET T3R ; start timer T3
WStpB: JNB P3.11,WStpB ; wait for stop bit at RXD0
BCLR T3R ; stop timer T3
MOV MDL,T3
SUB MDL,#18 ; rounding & adjustment
MOV R1,#36 ; baudrate = (T3 / 36) - 1
DIVU R1
MOV S0BG,MDL ; load baudrate generator
MOV S0CON,#8011H ; SET SERIAL MODE
MOV T3,#0 ; Clear timer 3 register
MOV S0TBUF,#0FFH ; Send acknoledge byte for monitor
ELSE
; Fixed Baudrate
BG_RLOAD EQU (CPU_CLOCK / (32 * BAUDRATE)) - 1
MOV S0BG ,#BG_RLOAD ; SET BAUDRATE
MOV S0CON,#8011H ; SET SERIAL MODE
EXTR #01H ; Extended SFR access
MOV ALTSEL0P3, #0C00h; Configure port pins for serial interface
ENDIF
$ENDIF
JMP CC_UC,MON166
;********************************************************************
;* Basic Input Output Functions for serial Interface 0 *
;********************************************************************
INSTAT: BMOV R4.0,S0RIR ; INPUT STATUS OF SERIAL INTERFACE
RET
OUTSTAT: BMOV R4.0,S0TIR ; OUTPUT STATUS OF SERIAL INTERFACE
RET
INCHAR: MOV R4,S0RBUF ; CHARACTER INPUT-ROUTINE
RET
OUTCHAR: MOV S0TBUF,R4 ; CHARACTER OUTPUT-ROUTINE
RET
CLR_TI: BCLR S0TIR ; CLEAR SERIAL TRANSMIT INTERRUPT FLAG
RET
SET_TI: BSET S0TIR ; SET SERIAL TRANSMIT INTERRUPT FLAG
RET
CLR_RI: BCLR S0RIR ; CLEAR SERIAL RECEIVE INTERRUPT FLAG
RET
CLR_SER_IE: MOV S0RIC,#0000 ; CLR S0RIE AND ILVL=0
RET
SET_SER_IE: MOV S0RIC,#007CH ; SET S0RIE AND ILVL=15
RET
RD_RIE: BMOV R4.0,S0RIE ; READ RECEIVE INTERRUPT ENABLE FLAG
RET
RD_TIE: BMOV R4.0,S0TIE ; READ TRANSMIT INTERRUPT ENABLE FLAG
RET
WR_RIE: BMOV S0RIE,R4.0 ; WRITE RECEIVE INTERRUPT ENABLE FLAG
RET
WR_TIE: BMOV S0TIE,R4.0 ; WRITE TRANSMIT INTERRUPT ENABLE FLAG
RET
WR_RIR: BMOV S0RIR,R4.0 ; WRITE RECEIVE INTERRUPT ENABLE FLAG
RET
WR_TIR: BMOV S0TIR,R4.0 ; WRITE TRANSMIT INTERRUPT ENABLE FLAG
RET
BEFORE_GO: ; IS NOT USED
RET
AFTER_GO: ; IS NOT USED
RET
$ENDIF
$IF (SERIAL2)
;********************************************************************
;* Initialization of simulated Serial Interface 2 *
;********************************************************************
T_LINE BIT P3.9 ; Transmit Data Line TxD
T_OUT BIT DP3.9 ; Port direction register for TxD
R_LINE BIT P3.8 ; Receive Data Line RxD
R_IN BIT DP3.8 ; Port direction register for RxD
STATES_PER_BIT EQU (CPU_CLOCK / BAUDRATE)
BSET T_LINE ;
BSET T_OUT ; set TxD to output
BCLR R_IN ; set RxD to input
CALL AFTER_GO
JMP CC_UC,MON166
INSTAT: BSET R4.0 ; INPUT STATUS OF SERIAL INTERFACE
RET
OUTSTAT: BSET R4.0 ; OUTPUT STATUS OF SERIAL INTERFACE
RET
;*************** CHARACTER INPUT-ROUTINE ************************
INCHAR: PUSH R2
PUSH R3
MOV R3,#8 ; Bit counter
MOV R4,#00H
STARTBIT: JNB R_LINE,STARTBIT ; Wait until last data bit is over
STARTBIT1: JB R_LINE,STARTBIT1; Wait for startbit
MOV R2,DPP0:C_VAR1 ; Startbit valid, begin sampling !
WAIT1: SUB R2,#1 ;
JMPR CC_NZ,WAIT1 ;
RECEIVE: BMOV R4.8,R_LINE ; Bit input
SHR R4,#1
SUB R3,#1
JMPR CC_Z,LASTBIT ; Last bit ?
MOV R2,DPP0:C_VAR2 ; Sample period generation
WAIT2: SUB R2,#1
JMPR CC_NZ,WAIT2
JMPR CC_UC,RECEIVE
LASTBIT: POP R3
POP R2
RET
;*************** CHARACTER OUTPUT-ROUTINE *******************
OUTCHAR: PUSH R2
PUSH R3
PUSH R4
OR R4,#0100H ; Insert stopbit
SHL R4,#1 ; Insert startbit
MOV R3,#10 ; Bit counter
NEXTBIT: ASHR R4,#1
BMOV T_LINE,C ; Bit output
MOV R2,DPP0:C_VAR3
WAIT: SUB R2,#1
JMPR CC_NZ,WAIT ; Baud rate generation
SUB R3,#1
JMPR CC_NZ,NEXTBIT ; Last bit ?
POP R4 ; Yes
POP R3
POP R2
RET
CLR_TI: RET ; IS NOT USED
SET_TI: RET ; IS NOT USED
CLR_RI: RET ; IS NOT USED
CLR_SER_IE: RET ; IS NOT USED
SET_SER_IE: RET ; IS NOT USED
RD_RIE: RET ; IS NOT USED
RD_TIE: RET ; IS NOT USED
WR_RIE: RET ; IS NOT USED
WR_TIE: RET ; IS NOT USED
WR_RIR: RET ; IS NOT USED
WR_TIR: RET ; IS NOT USED
BEFORE_GO: RET ; IS NOT USED
AFTER_GO: MOV DPP0,#PAG MON166_W_DATA
MOV R1,DPP3:BUSCON0 ; Programmed number of waitstates
AND R1,#000FH
MOV R2,#15
SUB R2,R1 ; ACT = State times for one
ADD R2,#3 ; external memory access
MOV R1,DPP3:BUSCON0
SHR R1,#5
AND R1,#0001H
SUB R2,R1
JNB BUSCON0.6,NMBUS
ADD R2,#1 ; Multiplexed bus
NMBUS: MOV R3,#14 ; Non-multiplexed bus
JB BUSCON0.7,BIT_16_1
ADD R3,#13 ; 8-Bit bus (16 ACTs)
BIT_16_1: MOV R13,#STATES_PER_BIT ; 16-Bit bus (8 ACTs)
MUL R3,R2 ;
SUB R13,MDL
SUB R13,#4
SHR R13,#2 ; Remaining states for loop
MOV DPP0:C_VAR2,R13
MOV R13,#STATES_PER_BIT ; Multiply by 1.5
MOV R3,R13
SHR R3,#1
ADD R13,R3
MOV R3,#11
JB BUSCON0.7,BIT_16_2
ADD R3,#14; ; 8-Bit Bus
BIT_16_2: MUL R3,R2
SUB R13,MDL
SUB R13,#2
SHR R13,#2
MOV DPP0:C_VAR1,R13
MOV R13,#STATES_PER_BIT
MOV R3,#13
JB BUSCON0.7,BIT_16_3
ADD R3,#10 ; 8-Bit Bus
BIT_16_3: MUL R3,R2
SUB R13,MDL
SUB R13,#4
SHR R13,#2
MOV DPP0:C_VAR3,R13
RET
$ENDIF
INSTALLCODE ENDP
INIT_CODE ENDS
END
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