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📄 boot_v2.a66

📁 TQ公司的STK16x开发系统的源码
💻 A66
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$MODV2					; Define XC166 C166v2 mode
$segmented

; Special Function Register Addresses
ADDRSEL1 EQU    0EE1EH
ADDRSEL2 EQU    0EE26H
ADDRSEL3 EQU    0EE2EH
ADDRSEL4 EQU    0EE36H
ADDRSEL5 EQU    0EE3EH
ADDRSEL6 EQU    0EE46H
ADDRSEL7 EQU    0EE4EH
CPUCON1  DEFR   0FE18H
CPUCON2  DEFR   0FE1AH
EBCMOD0  EQU    0EE00H
EBCMOD1  EQU    0EE02H
FOCON    DEFR   0FFAAH
FCONCS0  EQU    0EE12H
FCONCS1  EQU    0EE1AH
FCONCS2  EQU    0EE22H
FCONCS3  EQU    0EE2AH
FCONCS4  EQU    0EE32H
FCONCS5  EQU    0EE3AH
FCONCS6  EQU    0EE42H
FCONCS7  EQU    0EE4AH
RSTCON   EQU    0F1E0H
SP       DEFR   0FE12H
SPSEG    DEFR   0FF0CH
STKOV    DEFR   0FE14H
STKUN    DEFR   0FE16H
SYSCON1  DEFR   0F1DCH
SYSCON3  DEFR   0F1D4H
PLLCON   DEFR   0F1D0H
TCONCS0  EQU    0EE10H
TCONCS1  EQU    0EE18H
TCONCS2  EQU    0EE20H
TCONCS3  EQU    0EE28H
TCONCS4  EQU    0EE30H
TCONCS5  EQU    0EE38H
TCONCS6  EQU    0EE40H
TCONCS7  EQU    0EE48H
VECSEG   DEFR   0FF12H
WDTCON   DEFR   0FFAEH

;* Serial Interface *
S0BG     DEFR	0FEB4H
S0CON    DEFR	0FFB0H
S0EIC    DEFR	0FF70H
S0RBUF   DEFR	0FEB2H
S0RIC    DEFR	0FF6EH
S0TBUF   DEFR	0FEB0H
S0TBIC   DEFR	0F19CH
S0TIC    DEFR	0FF6CH
S0STP    BIT	S0CON.3
S0REN    BIT	S0CON.4
S0PEN    BIT	S0CON.5
S0FEN    BIT	S0CON.6
S0OEN    BIT	S0CON.7
S0PE     BIT	S0CON.8
S0FE     BIT	S0CON.9
S0OE     BIT	S0CON.10
S0ODD    BIT	S0CON.12
S0BRS    BIT	S0CON.13
S0LB     BIT	S0CON.14
S0R      BIT	S0CON.15
S0TIE    BIT	S0TIC.6
S0TIR    BIT	S0TIC.7
S0TBIE   BIT	S0TBIC.6
S0TBIR   BIT	S0TBIC.7
S0RIE    BIT	S0RIC.6
S0RIR    BIT	S0RIC.7
S0EIE    BIT	S0EIC.6
S0EIR    BIT	S0EIC.7



; Settings for ADDRSEL calculation (do not change!)
KB          EQU    0x400     ; define KB constant for CS _SIZE calculation
MB          EQU    0x400*KB  ; define MB as 1024KB

;
;-----------------------------------------------------------------------------
;  This file is part of the C166 Compiler package
;  Copyright KEIL ELEKTRONIK GmbH 1993 - 2001
;-----------------------------------------------------------------------------
;  BOOT_V2.A66:  This code is executed after processor reset when the
;                bootstrap mode is enabled and provides the initialization
;                of the XC166/Super10 processor and downloading of MONITOR.
;
;-----------------------------------------------------------------------------
;
; Definitions for SYSCON and BUSCON0 Register:
; --------------------------------------------

$INCLUDE (ConfigV2.INC)

INT_ADR_SEG EQU %VECTAB >> 16	    ; Interrupt Vector offset if MONITOR 166

                SSKDEF  7           ; unlimited System stack size

WR_MEM		EQU	1	; write memory
GO_COMMAND	EQU	6	; go command
GET_MON_SUM	EQU	16	; get monitor checksum

E_NOERROR	EQU	0	; no error                     ACK
E_UNKNOWN	EQU	1	; unknown command              len = 1
E_CHECKSUM	EQU	2	; checksum error               len = 1
E_NORAM		EQU	3	; no RAM at address            len = 4

STX		EQU	02H	; Start of TeXt
ENQ		EQU	05H	; ENQuiry
ACK		EQU	06H	; ACKnowledge
DC1		EQU	11H	; Ctrl+Q
NACK		EQU	15H	; Negative ACKnowledge

; Historic Parameter for old CPU's
; BOOT960 = 0: C167 CPU with 32 Byte Bootstrap loader is used
; BOOT960 = 1: C167 CPU with 960 Byte Bootstrap loader is used
$SET (BOOT960 = 0)
                 ASSUME  DPP3 : SYSTEM
 

BOOTSTRAP  SECTION CODE AT 0E00000H

BOOT		PROC	NEAR
START:		DISWDT
                MOV	R0,#0020H		; Start of bootstrap code
                MOV     DPP0,#PAG START2
LAB2:		BCLR	S0RIR
LAB1:		JNB	S0RIR,LAB1		; when CPU expects 32 Bytes
		MOVB	[R0],S0RBUF
		CMPI1	R0,#SOF(ENDBOOT)-1
		JMPR	CC_NZ,LAB2
                JMP     START2
BOOT            ENDP

START2          PROC    FAR
		MOV	CP,#0F7D0H
		MOV	STKOV,#0F600H
		MOV	STKUN,#0F7D0H
		MOV     SP,#0F7D0H		; at address 0FA60H

                BCLR    S0RIR
                BSET    S0TIR

		MOV	DPP0,#0000H
		MOV	DPP1,#0001H
		MOV	DPP2,#0002H
		MOV	DPP3,#0003H

;------------------------------------------------------------------------------


; Macro for calculation of ADDRSEL values -------------

CALC_ADDRSEL     MACRO   sym, adr, size
IF     size <= (4*KB)
sym             EQU     ((adr >> 8) AND 0xFFF0) OR 0
ELSEIF size <= (8*KB)
sym             EQU     ((adr >> 8) AND 0xFFE0) OR 1
ELSEIF size <= (16*KB)
sym             EQU     ((adr >> 8) AND 0xFFC0) OR 2
ELSEIF size <= (32*KB)
sym             EQU     ((adr >> 8) AND 0xFF80) OR 3
ELSEIF size <= (64*KB)
sym             EQU     ((adr >> 8) AND 0xFF00) OR 4
ELSEIF size <= (128*KB)
sym             EQU     ((adr >> 8) AND 0xFE00) OR 5
ELSEIF size <= (256*KB)
sym             EQU     ((adr >> 8) AND 0xFC00) OR 6
ELSEIF size <= (512*KB)
sym             EQU     ((adr >> 8) AND 0xF800) OR 7
ELSEIF size <= (1*MB)
sym             EQU     ((adr >> 8) AND 0xF000) OR 8
ELSEIF size <= (2*MB)
sym             EQU     ((adr >> 8) AND 0xE000) OR 9
ELSEIF size <= (4*MB)
sym             EQU     ((adr >> 8) AND 0xC000) OR 10
ELSEIF size <= (8*MB)
sym             EQU     ((adr >> 8) AND 0x8000) OR 11
ENDIF
                ENDM
; -----------------------------------------------------

                                        ; Set CPUCON1 register
_CPC1           SET     (_VECSC<<5) OR (_WDTCTL<<4) OR (_SGTDIS<<3) 
_CPC1           SET     _CPC1 OR (_INTSCXT<<2) OR (_BP<<1) OR (_ZCJ)
                MOV     CPUCON1,#_CPC1

$IF (INIT_CPUCON2 = 1)                  ; Set CPUCON2 register
_CPC2           SET     (_RETST<<3) OR (_FASTBL<<2) OR (_FASTPEC<<1) OR (_SL)
_CPC2           SET     _CPC2 OR (_EIOIAEN<<7) OR (_STEN<<6) OR (_ZSC<<5) OR (_OVRUN<<4)
_CPC2           SET     _CPC2 OR (_BYPPF<<9) OR (_BYPF<<8) 
_CPC2           SET     _CPC2 OR (_FIFODEPTH<<12) OR (_FIFOFED<<10) 
                MOV     CPUCON2,#_CPC2
$ENDIF

$IF (INIT_SYSCON1 = 1)                  ; Set SYSCON1 register
_SYSC1          SET     (_CPSYS<<8) OR (_PFCFG<<4) OR (_PDCFG<<2) OR (_SLEEPCON)
                EXTR    #01H            ; Extended SFR access
                MOV     SYSCON1,#_SYSC1         
$ENDIF

$IF (INIT_SYSCON3 = 1)                  ; Set SYSCON3 register
_SYSC3          SET     ADCDIS OR (ASC0DIS << 1)  OR (SSC0DIS << 2)  OR (GPTDIS << 3)
_SYSC3          SET     _SYSC3 OR (FMDIS << 5)    OR (CC1DIS << 6)   OR (CC2DIS << 7)
_SYSC3          SET     _SYSC3 OR (CC6DIS << 8)   OR (ASC1DIS << 10) OR (I2CDIS << 11)
_SYSC3          SET     _SYSC3 OR (SDLMDIS << 12) OR (CANDIS  << 13) OR (SSC1DIS<< 15)
                EXTR    #1
                MOV     SYSCON3,#_SYSC3
$ENDIF

$IF (CONFIG_EBC = 1)                    ; Set EBCMOD0 register
_EBC0           SET     (_SLAVE<<9) OR (_ARBEN<<8) OR (_CSPEN<<4) OR (_SAPEN)
_EBC0           SET     _EBC0 OR (_BYTDIS<<12) OR (_WRCFG<<11)  OR (_EBCDIS<<10) 
_EBC0           SET     _EBC0 OR (_RDYPOL<<15) OR (_RDYDIS<<14) OR (_ALEDIS<<13)
                MOV     R0,#_EBC0
                MOV     EBCMOD0,R0

                                        ; Set EBCMOD1 register
_EBC1           SET  (_DHPDIS<<6) OR (_APDIS)
                MOV     R0,#_EBC1
                MOV     EBCMOD1,R0
$ENDIF

$IF (CONFIG_CS0)  
                                        ; Set TCONCS0 register
_TCS0           SET     (_PHD0<<5) OR (_PHC0<<3) OR (_PHB0<<2) OR (_PHA0)
_TCS0           SET     _TCS0 OR (_WRPHF0<<13) OR (_RDPHF0<<11) OR (_PHE0<<6)
                MOV     R0,#_TCS0
                MOV     TCONCS0,R0
                                        ; Set FCONCS0 register
_FCS0  SET  (_BTYP0<<4) OR (_RDYMOD0<<2) OR (_RDYEN0<<1) OR (_ENCS0)
                MOV     R0,#_FCS0
                MOV     FCONCS0,R0
$ENDIF

$IF (CONFIG_CS1)  
                                        ; Set TCONCS1 register
_TCS1           SET     (_PHD1<<5) OR (_PHC1<<3) OR (_PHB1<<2) OR (_PHA1)
_TCS1           SET     _TCS1 OR (_WRPHF1<<13) OR (_RDPHF1<<11) OR (_PHE1<<6)
                MOV     R0,#_TCS1
                MOV     TCONCS1,R0
                                        ; Set ADDRSEL1 register
CALC_ADDRSEL    _ADDRSEL1, _ADDR1, _SIZE1
                MOV     R0,#_ADDRSEL1
                MOV     ADDRSEL1,R0
                                        ; Set FCONCS1 register
_FCS1  SET  (_BTYP1<<4) OR (_RDYMOD1<<2) OR (_RDYEN1<<1) OR (_ENCS1)
                MOV     R0,#_FCS1
                MOV     FCONCS1,R0

$ENDIF

$IF (CONFIG_CS2)  
                                        ; Set TCONCS2 register
_TCS2           SET     (_PHD2<<5) OR (_PHC2<<3) OR (_PHB2<<2) OR (_PHA2)
_TCS2           SET     _TCS2 OR (_WRPHF2<<13) OR (_RDPHF2<<11) OR (_PHE2<<6)
                MOV     R0,#_TCS2
                MOV     TCONCS2,R0
                                        ; Set ADDRSEL2 register
CALC_ADDRSEL    _ADDRSEL2, _ADDR2, _SIZE2
                MOV     R0,#_ADDRSEL2
                MOV     ADDRSEL2,R0

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