📄 output.vho
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signal GATE_T_49_A : std_logic;
begin
IN_adresse_5_I_1: IBUF port map ( O=>adresse_5XPIN, I0=>adresse(5) );
OUT_p2_7_I_1: OBUF port map ( O=>p2(7), I0=>p2_7XCOM );
OUT_p7_3_I_1: OBUF port map ( O=>p7(3), I0=>p7_3XCOM );
OUT_p8_7_I_1: OBUF port map ( O=>p8(7), I0=>p8_7XCOM );
IN_reset_I_1: IBUF port map ( O=>resetPIN, I0=>reset );
IN_rd_I_1: IBUF port map ( O=>rdPIN, I0=>rd );
IN_wr_I_1: IBUF port map ( O=>wrPIN, I0=>wr );
IN_cs_I_1: IBUF port map ( O=>csPIN, I0=>cs );
IN_adresse_4_I_1: IBUF port map ( O=>adresse_4XPIN, I0=>adresse(4) );
IN_adresse_3_I_1: IBUF port map ( O=>adresse_3XPIN, I0=>adresse(3) );
IN_adresse_2_I_1: IBUF port map ( O=>adresse_2XPIN, I0=>adresse(2) );
IN_adresse_1_I_1: IBUF port map ( O=>adresse_1XPIN, I0=>adresse(1) );
IN_adresse_0_I_1: IBUF port map ( O=>adresse_0XPIN, I0=>adresse(0) );
OUT_p2_6_I_1: OBUF port map ( O=>p2(6), I0=>p2_6XCOM );
OUT_p2_5_I_1: OBUF port map ( O=>p2(5), I0=>p2_5XCOM );
OUT_p2_4_I_1: OBUF port map ( O=>p2(4), I0=>p2_4XCOM );
OUT_p2_3_I_1: OBUF port map ( O=>p2(3), I0=>p2_3XCOM );
OUT_p2_2_I_1: OBUF port map ( O=>p2(2), I0=>p2_2XCOM );
OUT_p2_1_I_1: OBUF port map ( O=>p2(1), I0=>p2_1XCOM );
OUT_p2_0_I_1: OBUF port map ( O=>p2(0), I0=>p2_0XCOM );
OUT_p7_2_I_1: OBUF port map ( O=>p7(2), I0=>p7_2XCOM );
OUT_p7_1_I_1: OBUF port map ( O=>p7(1), I0=>p7_1XCOM );
OUT_p7_0_I_1: OBUF port map ( O=>p7(0), I0=>p7_0XCOM );
OUT_p8_6_I_1: OBUF port map ( O=>p8(6), I0=>p8_6XCOM );
OUT_data_7_I_1: BI_DIR port map ( O=>data_7XPIN, I0=>data_7XQ, IO=>data(7), OE=>un1_un1_data_p821Q );
OUT_data_6_I_1: BI_DIR port map ( O=>data_6XPIN, I0=>data_6XQ, IO=>data(6), OE=>un1_un1_data_p821Q );
OUT_data_5_I_1: BI_DIR port map ( O=>data_5XPIN, I0=>data_5XQ, IO=>data(5), OE=>un1_un1_data_p821Q );
OUT_data_4_I_1: BI_DIR port map ( O=>data_4XPIN, I0=>data_4XQ, IO=>data(4), OE=>un1_un1_data_p821Q );
OUT_data_3_I_1: BI_DIR port map ( O=>data_3XPIN, I0=>data_3XQ, IO=>data(3), OE=>un1_un1_data_p821Q );
OUT_data_2_I_1: BI_DIR port map ( O=>data_2XPIN, I0=>data_2XQ, IO=>data(2), OE=>un1_un1_data_p821Q );
OUT_data_1_I_1: BI_DIR port map ( O=>data_1XPIN, I0=>data_1XQ, IO=>data(1), OE=>un1_un1_data_p821Q );
OUT_data_0_I_1: BI_DIR port map ( O=>data_0XPIN, I0=>data_0XQ, IO=>data(0), OE=>un1_un1_data_p821Q );
LATCH_data_7_I_I: DLATRH port map ( Q=>data_7XQ, LAT=>data_7X_LH, R=>data_7X_AR, D=>data_7X_D );
LATCH_data_6_I_I: DLATRH port map ( Q=>data_6XQ, LAT=>data_6X_LH, R=>data_6X_AR, D=>data_6X_D );
LATCH_data_5_I_I: DLATRH port map ( Q=>data_5XQ, LAT=>data_5X_LH, R=>data_5X_AR, D=>data_5X_D );
LATCH_data_4_I_I: DLATRH port map ( Q=>data_4XQ, LAT=>data_4X_LH, R=>data_4X_AR, D=>data_4X_D );
LATCH_data_3_I_I: DLATRH port map ( Q=>data_3XQ, LAT=>data_3X_LH, R=>data_3X_AR, D=>data_3X_D );
LATCH_data_2_I_I: DLATRH port map ( Q=>data_2XQ, LAT=>data_2X_LH, R=>data_2X_AR, D=>data_2X_D );
LATCH_data_1_I_I: DLATRH port map ( Q=>data_1XQ, LAT=>data_1X_LH, R=>data_1X_AR, D=>data_1X_D );
LATCH_data_0_I_I: DLATRH port map ( Q=>data_0XQ, LAT=>data_0X_LH, R=>data_0X_AR, D=>data_0X_D );
LATCH_un1_un1_data_p821_I_I: DLATRH port map ( Q=>un1_un1_data_p821Q, LAT=>un1_un1_data_p821_LH, R=>un1_un1_data_p821_AR, D=>un1_un1_data_p821_D );
LATCH_data_p7_0_I_1: DLAT port map ( Q=>data_p7_0Q, LAT=>data_p7_0_LH, D=>data_p7_0_D );
LATCH_data_p7_1_I_1: DLAT port map ( Q=>data_p7_1Q, LAT=>data_p7_0_LH, D=>data_p7_1_D );
LATCH_data_p7_2_I_1: DLAT port map ( Q=>data_p7_2Q, LAT=>data_p7_0_LH, D=>data_p7_2_D );
LATCH_data_p7_3_I_1: DLAT port map ( Q=>data_p7_3Q, LAT=>data_p7_0_LH, D=>data_p7_3_D );
LATCH_data_p2_0_I_1: DLAT port map ( Q=>data_p2_0Q, LAT=>data_p2_0_LH, D=>data_p2_0_D );
LATCH_data_p2_1_I_1: DLAT port map ( Q=>data_p2_1Q, LAT=>data_p2_0_LH, D=>data_p2_1_D );
LATCH_data_p2_2_I_1: DLAT port map ( Q=>data_p2_2Q, LAT=>data_p2_0_LH, D=>data_p2_2_D );
LATCH_data_p2_3_I_1: DLAT port map ( Q=>data_p2_3Q, LAT=>data_p2_0_LH, D=>data_p2_3_D );
LATCH_data_p2_4_I_1: DLAT port map ( Q=>data_p2_4Q, LAT=>data_p2_0_LH, D=>data_p2_4_D );
LATCH_data_p2_5_I_1: DLAT port map ( Q=>data_p2_5Q, LAT=>data_p2_0_LH, D=>data_p2_5_D );
LATCH_data_p2_6_I_1: DLAT port map ( Q=>data_p2_6Q, LAT=>data_p2_0_LH, D=>data_p2_6_D );
LATCH_data_p2_7_I_1: DLAT port map ( Q=>data_p2_7Q, LAT=>data_p2_0_LH, D=>data_p2_7_D );
LATCH_data_p8_6_I_1: DLAT port map ( Q=>data_p8_6Q, LAT=>data_p8_6_LH, D=>data_p8_6_D );
LATCH_data_p8_7_I_1: DLAT port map ( Q=>data_p8_7Q, LAT=>data_p8_6_LH, D=>data_p8_7_D );
GATE_p2_7_I_1: AND2 port map ( O=>p2_7XCOM, I1=>data_p2_7Q, I0=>resetPIN );
GATE_p7_3_I_1: AND2 port map ( O=>p7_3XCOM, I1=>data_p7_3Q, I0=>resetPIN );
GATE_p8_7_I_1: AND2 port map ( O=>p8_7XCOM, I1=>data_p8_7Q, I0=>resetPIN );
GATE_p2_6_I_1: AND2 port map ( O=>p2_6XCOM, I1=>data_p2_6Q, I0=>resetPIN );
GATE_p2_5_I_1: AND2 port map ( O=>p2_5XCOM, I1=>data_p2_5Q, I0=>resetPIN );
GATE_p2_4_I_1: AND2 port map ( O=>p2_4XCOM, I1=>data_p2_4Q, I0=>resetPIN );
GATE_p2_3_I_1: AND2 port map ( O=>p2_3XCOM, I1=>data_p2_3Q, I0=>resetPIN );
GATE_p2_2_I_1: AND2 port map ( O=>p2_2XCOM, I1=>data_p2_2Q, I0=>resetPIN );
GATE_p2_1_I_1: AND2 port map ( O=>p2_1XCOM, I1=>data_p2_1Q, I0=>resetPIN );
GATE_p2_0_I_1: AND2 port map ( O=>p2_0XCOM, I1=>data_p2_0Q, I0=>resetPIN );
GATE_p7_2_I_1: AND2 port map ( O=>p7_2XCOM, I1=>data_p7_2Q, I0=>resetPIN );
GATE_p7_1_I_1: AND2 port map ( O=>p7_1XCOM, I1=>data_p7_1Q, I0=>resetPIN );
GATE_p7_0_I_1: AND2 port map ( O=>p7_0XCOM, I1=>data_p7_0Q, I0=>resetPIN );
GATE_p8_6_I_1: AND2 port map ( O=>p8_6XCOM, I1=>data_p8_6Q, I0=>resetPIN );
GATE_data_7X_D_I_1: OR2 port map ( O=>data_7X_D, I1=>T_18, I0=>T_17 );
GATE_data_7X_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>data_7X_LH );
GATE_data_7X_AR_I_1: INV port map ( I0=>resetPIN, O=>data_7X_AR );
GATE_data_6X_D_I_1: OR2 port map ( O=>data_6X_D, I1=>T_14, I0=>T_13 );
GATE_data_6X_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>data_6X_LH );
GATE_data_6X_AR_I_1: INV port map ( I0=>resetPIN, O=>data_6X_AR );
GATE_data_5X_D_I_1: AND4 port map ( O=>data_5X_D, I3=>T_39, I2=>T_40, I1=>T_41, I0=>data_p2_5Q );
GATE_data_5X_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>data_5X_LH );
GATE_data_5X_AR_I_1: INV port map ( I0=>resetPIN, O=>data_5X_AR );
GATE_data_4X_D_I_1: AND4 port map ( O=>data_4X_D, I3=>T_36, I2=>T_37, I1=>T_38, I0=>data_p2_4Q );
GATE_data_4X_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>data_4X_LH );
GATE_data_4X_AR_I_1: INV port map ( I0=>resetPIN, O=>data_4X_AR );
GATE_data_3X_D_I_1: OR2 port map ( O=>data_3X_D, I1=>T_12, I0=>T_11 );
GATE_data_3X_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>data_3X_LH );
GATE_data_3X_AR_I_1: INV port map ( I0=>resetPIN, O=>data_3X_AR );
GATE_data_2X_D_I_1: OR2 port map ( O=>data_2X_D, I1=>T_10, I0=>T_9 );
GATE_data_2X_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>data_2X_LH );
GATE_data_2X_AR_I_1: INV port map ( I0=>resetPIN, O=>data_2X_AR );
GATE_data_1X_D_I_1: OR2 port map ( O=>data_1X_D, I1=>T_8, I0=>T_7 );
GATE_data_1X_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>data_1X_LH );
GATE_data_1X_AR_I_1: INV port map ( I0=>resetPIN, O=>data_1X_AR );
GATE_data_0X_D_I_1: OR2 port map ( O=>data_0X_D, I1=>T_6, I0=>T_5 );
GATE_data_0X_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>data_0X_LH );
GATE_data_0X_AR_I_1: INV port map ( I0=>resetPIN, O=>data_0X_AR );
GATE_un1_un1_data_p821_D_I_1: OR2 port map ( O=>un1_un1_data_p821_D, I1=>T_4, I0=>T_3 );
GATE_un1_un1_data_p821_LH_I_1: INV port map ( I0=>Port_sel_un109_data_iZ0, O=>un1_un1_data_p821_LH );
GATE_un1_un1_data_p821_AR_I_1: INV port map ( I0=>resetPIN, O=>un1_un1_data_p821_AR );
GATE_data_p7_0_D_I_1: AND2 port map ( O=>data_p7_0_D, I1=>data_0XPIN, I0=>resetPIN );
GATE_data_p7_1_D_I_1: AND2 port map ( O=>data_p7_1_D, I1=>data_1XPIN, I0=>resetPIN );
GATE_data_p7_2_D_I_1: AND2 port map ( O=>data_p7_2_D, I1=>data_2XPIN, I0=>resetPIN );
GATE_data_p7_3_D_I_1: AND2 port map ( O=>data_p7_3_D, I1=>data_3XPIN, I0=>resetPIN );
GATE_data_p2_0_D_I_1: AND2 port map ( O=>data_p2_0_D, I1=>data_0XPIN, I0=>resetPIN );
GATE_data_p2_1_D_I_1: AND2 port map ( O=>data_p2_1_D, I1=>data_1XPIN, I0=>resetPIN );
GATE_data_p2_2_D_I_1: AND2 port map ( O=>data_p2_2_D, I1=>data_2XPIN, I0=>resetPIN );
GATE_data_p2_3_D_I_1: AND2 port map ( O=>data_p2_3_D, I1=>data_3XPIN, I0=>resetPIN );
GATE_data_p2_4_D_I_1: AND2 port map ( O=>data_p2_4_D, I1=>data_4XPIN, I0=>resetPIN );
GATE_data_p2_5_D_I_1: AND2 port map ( O=>data_p2_5_D, I1=>data_5XPIN, I0=>resetPIN );
GATE_data_p2_6_D_I_1: AND2 port map ( O=>data_p2_6_D, I1=>data_6XPIN, I0=>resetPIN );
GATE_data_p2_7_D_I_1: AND2 port map ( O=>data_p2_7_D, I1=>data_7XPIN, I0=>resetPIN );
GATE_data_p8_6_D_I_1: AND2 port map ( O=>data_p8_6_D, I1=>data_6XPIN, I0=>resetPIN );
GATE_data_p8_7_D_I_1: AND2 port map ( O=>data_p8_7_D, I1=>data_7XPIN, I0=>resetPIN );
GATE_data_p2_0_LH_I_1: NAN2 port map ( O=>data_p2_0_LH, I0=>resetPIN, I1=>GATE_data_p2_0_LH_A );
GATE_data_p2_0_LH_I_2: INV port map ( O=>GATE_data_p2_0_LH_A, I0=>T_1 );
GATE_data_p7_0_LH_I_1: NAN2 port map ( O=>data_p7_0_LH, I0=>resetPIN, I1=>GATE_data_p7_0_LH_A );
GATE_data_p7_0_LH_I_2: INV port map ( O=>GATE_data_p7_0_LH_A, I0=>T_2 );
GATE_Port_sel_un109_data_iZ0_I_1: OR2 port map ( O=>Port_sel_un109_data_iZ0, I1=>T_16, I0=>T_15 );
GATE_data_p8_6_LH_I_1: NAN2 port map ( O=>data_p8_6_LH, I0=>resetPIN, I1=>GATE_data_p8_6_LH_A );
GATE_data_p8_6_LH_I_2: INV port map ( O=>GATE_data_p8_6_LH_A, I0=>T_0 );
GATE_T_0_I_1: AND3 port map ( O=>T_0, I2=>T_20, I1=>T_21, I0=>T_19 );
GATE_T_1_I_1: AND3 port map ( O=>T_1, I2=>T_23, I1=>T_24, I0=>T_22 );
GATE_T_2_I_1: AND3 port map ( O=>T_2, I2=>T_26, I1=>T_27, I0=>T_25 );
GATE_T_3_I_1: AND4 port map ( O=>T_3, I3=>T_32, I2=>T_33, I1=>T_34, I0=>T_35 );
GATE_T_4_I_1: AND4 port map ( O=>T_4, I3=>T_28, I2=>T_29, I1=>T_30, I0=>T_31 );
GATE_T_5_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_5_A );
GATE_T_5_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_5_B );
GATE_T_5_I_3: AND3 port map ( O=>T_5, I0=>data_p2_0Q, I2=>GATE_T_5_A, I1=>GATE_T_5_B );
GATE_T_6_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_6_A );
GATE_T_6_I_2: AND3 port map ( O=>T_6, I2=>adresse_0XPIN, I1=>data_p7_0Q, I0=>GATE_T_6_A );
GATE_T_7_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_7_A );
GATE_T_7_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_7_B );
GATE_T_7_I_3: AND3 port map ( O=>T_7, I0=>data_p2_1Q, I2=>GATE_T_7_A, I1=>GATE_T_7_B );
GATE_T_8_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_8_A );
GATE_T_8_I_2: AND3 port map ( O=>T_8, I2=>adresse_0XPIN, I1=>data_p7_1Q, I0=>GATE_T_8_A );
GATE_T_9_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_9_A );
GATE_T_9_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_9_B );
GATE_T_9_I_3: AND3 port map ( O=>T_9, I0=>data_p2_2Q, I2=>GATE_T_9_A, I1=>GATE_T_9_B );
GATE_T_10_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_10_A );
GATE_T_10_I_2: AND3 port map ( O=>T_10, I2=>adresse_0XPIN, I1=>data_p7_2Q, I0=>GATE_T_10_A );
GATE_T_11_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_11_A );
GATE_T_11_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_11_B );
GATE_T_11_I_3: AND3 port map ( O=>T_11, I0=>data_p2_3Q, I2=>GATE_T_11_A, I1=>GATE_T_11_B );
GATE_T_12_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_12_A );
GATE_T_12_I_2: AND3 port map ( O=>T_12, I2=>adresse_0XPIN, I1=>data_p7_3Q, I0=>GATE_T_12_A );
GATE_T_13_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_13_A );
GATE_T_13_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_13_B );
GATE_T_13_I_3: AND3 port map ( O=>T_13, I0=>data_p2_6Q, I2=>GATE_T_13_A, I1=>GATE_T_13_B );
GATE_T_14_I_1: AND2 port map ( O=>T_14, I1=>data_p8_6Q, I0=>adresse_1XPIN );
GATE_T_15_I_1: AND4 port map ( O=>T_15, I3=>T_46, I2=>T_47, I1=>T_48, I0=>T_49 );
GATE_T_16_I_1: AND4 port map ( O=>T_16, I3=>T_42, I2=>T_43, I1=>T_44, I0=>T_45 );
GATE_T_17_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_17_A );
GATE_T_17_I_2: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_17_B );
GATE_T_17_I_3: AND3 port map ( O=>T_17, I0=>data_p2_7Q, I2=>GATE_T_17_A, I1=>GATE_T_17_B );
GATE_T_18_I_1: AND2 port map ( O=>T_18, I1=>data_p8_7Q, I0=>adresse_1XPIN );
GATE_T_19_I_1: INV port map ( I0=>adresse_0XPIN, O=>GATE_T_19_A );
GATE_T_19_I_2: INV port map ( I0=>adresse_2XPIN, O=>GATE_T_19_B );
GATE_T_19_I_3: AND3 port map ( O=>T_19, I0=>adresse_1XPIN, I2=>GATE_T_19_A, I1=>GATE_T_19_B );
GATE_T_20_I_1: INV port map ( I0=>adresse_4XPIN, O=>GATE_T_20_A );
GATE_T_20_I_2: INV port map ( I0=>csPIN, O=>GATE_T_20_B );
GATE_T_20_I_3: AND3 port map ( O=>T_20, I0=>adresse_3XPIN, I2=>GATE_T_20_A, I1=>GATE_T_20_B );
GATE_T_21_I_1: INV port map ( I0=>wrPIN, O=>GATE_T_21_A );
GATE_T_21_I_2: INV port map ( I0=>adresse_5XPIN, O=>GATE_T_21_B );
GATE_T_21_I_3: AND3 port map ( O=>T_21, I0=>rdPIN, I2=>GATE_T_21_A, I1=>GATE_T_21_B );
GATE_T_22_I_1: NOR3 port map ( O=>T_22, I2=>adresse_1XPIN, I1=>adresse_2XPIN, I0=>adresse_0XPIN );
GATE_T_23_I_1: INV port map ( I0=>adresse_4XPIN, O=>GATE_T_23_A );
GATE_T_23_I_2: INV port map ( I0=>csPIN, O=>GATE_T_23_B );
GATE_T_23_I_3: AND3 port map ( O=>T_23, I0=>adresse_3XPIN, I2=>GATE_T_23_A, I1=>GATE_T_23_B );
GATE_T_24_I_1: INV port map ( I0=>wrPIN, O=>GATE_T_24_A );
GATE_T_24_I_2: INV port map ( I0=>adresse_5XPIN, O=>GATE_T_24_B );
GATE_T_24_I_3: AND3 port map ( O=>T_24, I0=>rdPIN, I2=>GATE_T_24_A, I1=>GATE_T_24_B );
GATE_T_25_I_1: INV port map ( I0=>adresse_1XPIN, O=>GATE_T_25_A );
GATE_T_25_I_2: INV port map ( I0=>adresse_2XPIN, O=>GATE_T_25_B );
GATE_T_25_I_3: AND3 port map ( O=>T_25, I0=>adresse_0XPIN, I2=>GATE_T_25_A, I1=>GATE_T_25_B );
GATE_T_26_I_1: INV port map ( I0=>adresse_4XPIN, O=>GATE_T_26_A );
GATE_T_26_I_2: INV port map ( I0=>csPIN, O=>GATE_T_26_B );
GATE_T_26_I_3: AND3 port map ( O=>T_26, I0=>adresse_3XPIN, I2=>GATE_T_26_A, I1=>GATE_T_26_B );
GATE_T_27_I_1: INV port map ( I0=>wrPIN, O=>GATE_T_27_A );
GATE_T_27_I_2: INV port map ( I0=>adresse_5XPIN, O=>GATE_T_27_B );
GATE_T_27_I_3: AND3 port map ( O=>T_27, I0=>rdPIN, I2=>GATE_T_27_A, I1=>GATE_T_27_B );
GATE_T_28_I_1: NOR2 port map ( O=>T_28, I1=>adresse_1XPIN, I0=>adresse_2XPIN );
GATE_T_29_I_1: AND2 port map ( O=>T_29, I1=>adresse_3XPIN, I0=>GATE_T_29_A );
GATE_T_29_I_2: INV port map ( O=>GATE_T_29_A, I0=>adresse_4XPIN );
GATE_T_30_I_1: AND2 port map ( O=>T_30, I1=>wrPIN, I0=>GATE_T_30_A );
GATE_T_30_I_2: INV port map ( O=>GATE_T_30_A, I0=>csPIN );
GATE_T_31_I_1: NOR2 port map ( O=>T_31, I1=>rdPIN, I0=>adresse_5XPIN );
GATE_T_32_I_1: NOR2 port map ( O=>T_32, I1=>adresse_0XPIN, I0=>adresse_2XPIN );
GATE_T_33_I_1: AND2 port map ( O=>T_33, I1=>adresse_3XPIN, I0=>GATE_T_33_A );
GATE_T_33_I_2: INV port map ( O=>GATE_T_33_A, I0=>adresse_4XPIN );
GATE_T_34_I_1: AND2 port map ( O=>T_34, I1=>wrPIN, I0=>GATE_T_34_A );
GATE_T_34_I_2: INV port map ( O=>GATE_T_34_A, I0=>csPIN );
GATE_T_35_I_1: NOR2 port map ( O=>T_35, I1=>rdPIN, I0=>adresse_5XPIN );
GATE_T_36_I_1: NOR3 port map ( O=>T_36, I2=>adresse_1XPIN, I1=>adresse_2XPIN, I0=>adresse_0XPIN );
GATE_T_37_I_1: INV port map ( I0=>adresse_4XPIN, O=>GATE_T_37_A );
GATE_T_37_I_2: INV port map ( I0=>csPIN, O=>GATE_T_37_B );
GATE_T_37_I_3: AND3 port map ( O=>T_37, I0=>adresse_3XPIN, I2=>GATE_T_37_A, I1=>GATE_T_37_B );
GATE_T_38_I_1: INV port map ( I0=>rdPIN, O=>GATE_T_38_A );
GATE_T_38_I_2: INV port map ( I0=>adresse_5XPIN, O=>GATE_T_38_B );
GATE_T_38_I_3: AND3 port map ( O=>T_38, I0=>wrPIN, I2=>GATE_T_38_A, I1=>GATE_T_38_B );
GATE_T_39_I_1: NOR3 port map ( O=>T_39, I2=>adresse_1XPIN, I1=>adresse_2XPIN, I0=>adresse_0XPIN );
GATE_T_40_I_1: INV port map ( I0=>adresse_4XPIN, O=>GATE_T_40_A );
GATE_T_40_I_2: INV port map ( I0=>csPIN, O=>GATE_T_40_B );
GATE_T_40_I_3: AND3 port map ( O=>T_40, I0=>adresse_3XPIN, I2=>GATE_T_40_A, I1=>GATE_T_40_B );
GATE_T_41_I_1: INV port map ( I0=>rdPIN, O=>GATE_T_41_A );
GATE_T_41_I_2: INV port map ( I0=>adresse_5XPIN, O=>GATE_T_41_B );
GATE_T_41_I_3: AND3 port map ( O=>T_41, I0=>wrPIN, I2=>GATE_T_41_A, I1=>GATE_T_41_B );
GATE_T_42_I_1: NOR2 port map ( O=>T_42, I1=>adresse_1XPIN, I0=>adresse_2XPIN );
GATE_T_43_I_1: AND2 port map ( O=>T_43, I1=>adresse_3XPIN, I0=>GATE_T_43_A );
GATE_T_43_I_2: INV port map ( O=>GATE_T_43_A, I0=>adresse_4XPIN );
GATE_T_44_I_1: NOR2 port map ( O=>T_44, I1=>csPIN, I0=>wrPIN );
GATE_T_45_I_1: AND2 port map ( O=>T_45, I1=>rdPIN, I0=>GATE_T_45_A );
GATE_T_45_I_2: INV port map ( O=>GATE_T_45_A, I0=>adresse_5XPIN );
GATE_T_46_I_1: NOR2 port map ( O=>T_46, I1=>adresse_0XPIN, I0=>adresse_2XPIN );
GATE_T_47_I_1: AND2 port map ( O=>T_47, I1=>adresse_3XPIN, I0=>GATE_T_47_A );
GATE_T_47_I_2: INV port map ( O=>GATE_T_47_A, I0=>adresse_4XPIN );
GATE_T_48_I_1: NOR2 port map ( O=>T_48, I1=>csPIN, I0=>wrPIN );
GATE_T_49_I_1: AND2 port map ( O=>T_49, I1=>rdPIN, I0=>GATE_T_49_A );
GATE_T_49_I_2: INV port map ( O=>GATE_T_49_A, I0=>adresse_5XPIN );
end NetList;
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