output.vho

TQ公司的STK16x开发系统的源码

-- VHDL netlist-file
library mach;
use mach.components.all;

library ieee;
use ieee.std_logic_1164.all;
entity Output_PLD is
  port (
    reset : in std_logic;
    rd : in std_logic;
    wr : in std_logic;
    cs : in std_logic;
    adresse : in std_logic_vector(5 downto 0);
    p2 : out std_logic_vector(7 downto 0);
    p7 : out std_logic_vector(3 downto 0);
    p8 : out std_logic_vector(7 downto 6);
    data : inout std_logic_vector(7 downto 0)
  );
end Output_PLD;

architecture NetList of Output_PLD is

  signal adresse_5XPIN : std_logic;
  signal p2_7XCOM : std_logic;
  signal p7_3XCOM : std_logic;
  signal p8_7XCOM : std_logic;
  signal resetPIN : std_logic;
  signal rdPIN : std_logic;
  signal wrPIN : std_logic;
  signal csPIN : std_logic;
  signal adresse_4XPIN : std_logic;
  signal adresse_3XPIN : std_logic;
  signal adresse_2XPIN : std_logic;
  signal adresse_1XPIN : std_logic;
  signal adresse_0XPIN : std_logic;
  signal p2_6XCOM : std_logic;
  signal p2_5XCOM : std_logic;
  signal p2_4XCOM : std_logic;
  signal p2_3XCOM : std_logic;
  signal p2_2XCOM : std_logic;
  signal p2_1XCOM : std_logic;
  signal p2_0XCOM : std_logic;
  signal p7_2XCOM : std_logic;
  signal p7_1XCOM : std_logic;
  signal p7_0XCOM : std_logic;
  signal p8_6XCOM : std_logic;
  signal data_7XPIN : std_logic;
  signal data_7XQ : std_logic;
  signal data_6XPIN : std_logic;
  signal data_6XQ : std_logic;
  signal data_5XPIN : std_logic;
  signal data_5XQ : std_logic;
  signal data_4XPIN : std_logic;
  signal data_4XQ : std_logic;
  signal data_3XPIN : std_logic;
  signal data_3XQ : std_logic;
  signal data_2XPIN : std_logic;
  signal data_2XQ : std_logic;
  signal data_1XPIN : std_logic;
  signal data_1XQ : std_logic;
  signal data_0XPIN : std_logic;
  signal data_0XQ : std_logic;
  signal un1_un1_data_p821Q : std_logic;
  signal data_p7_0Q : std_logic;
  signal data_p7_1Q : std_logic;
  signal data_p7_2Q : std_logic;
  signal data_p7_3Q : std_logic;
  signal data_p2_0Q : std_logic;
  signal data_p2_1Q : std_logic;
  signal data_p2_2Q : std_logic;
  signal data_p2_3Q : std_logic;
  signal data_p2_4Q : std_logic;
  signal data_p2_5Q : std_logic;
  signal data_p2_6Q : std_logic;
  signal data_p2_7Q : std_logic;
  signal data_p8_6Q : std_logic;
  signal data_p8_7Q : std_logic;
  signal data_7X_D : std_logic;
  signal data_7X_LH : std_logic;
  signal data_7X_AR : std_logic;
  signal data_6X_D : std_logic;
  signal data_6X_LH : std_logic;
  signal data_6X_AR : std_logic;
  signal data_5X_D : std_logic;
  signal data_5X_LH : std_logic;
  signal data_5X_AR : std_logic;
  signal data_4X_D : std_logic;
  signal data_4X_LH : std_logic;
  signal data_4X_AR : std_logic;
  signal data_3X_D : std_logic;
  signal data_3X_LH : std_logic;
  signal data_3X_AR : std_logic;
  signal data_2X_D : std_logic;
  signal data_2X_LH : std_logic;
  signal data_2X_AR : std_logic;
  signal data_1X_D : std_logic;
  signal data_1X_LH : std_logic;
  signal data_1X_AR : std_logic;
  signal data_0X_D : std_logic;
  signal data_0X_LH : std_logic;
  signal data_0X_AR : std_logic;
  signal un1_un1_data_p821_D : std_logic;
  signal un1_un1_data_p821_LH : std_logic;
  signal un1_un1_data_p821_AR : std_logic;
  signal data_p7_0_D : std_logic;
  signal data_p7_1_D : std_logic;
  signal data_p7_2_D : std_logic;
  signal data_p7_3_D : std_logic;
  signal data_p2_0_D : std_logic;
  signal data_p2_1_D : std_logic;
  signal data_p2_2_D : std_logic;
  signal data_p2_3_D : std_logic;
  signal data_p2_4_D : std_logic;
  signal data_p2_5_D : std_logic;
  signal data_p2_6_D : std_logic;
  signal data_p2_7_D : std_logic;
  signal data_p8_6_D : std_logic;
  signal data_p8_7_D : std_logic;
  signal data_p2_0_LH : std_logic;
  signal data_p7_0_LH : std_logic;
  signal Port_sel_un109_data_iZ0 : std_logic;
  signal data_p8_6_LH : std_logic;
  signal T_0 : std_logic;
  signal T_1 : std_logic;
  signal T_2 : std_logic;
  signal T_3 : std_logic;
  signal T_4 : std_logic;
  signal T_5 : std_logic;
  signal T_6 : std_logic;
  signal T_7 : std_logic;
  signal T_8 : std_logic;
  signal T_9 : std_logic;
  signal T_10 : std_logic;
  signal T_11 : std_logic;
  signal T_12 : std_logic;
  signal T_13 : std_logic;
  signal T_14 : std_logic;
  signal T_15 : std_logic;
  signal T_16 : std_logic;
  signal T_17 : std_logic;
  signal T_18 : std_logic;
  signal T_19 : std_logic;
  signal T_20 : std_logic;
  signal T_21 : std_logic;
  signal T_22 : std_logic;
  signal T_23 : std_logic;
  signal T_24 : std_logic;
  signal T_25 : std_logic;
  signal T_26 : std_logic;
  signal T_27 : std_logic;
  signal T_28 : std_logic;
  signal T_29 : std_logic;
  signal T_30 : std_logic;
  signal T_31 : std_logic;
  signal T_32 : std_logic;
  signal T_33 : std_logic;
  signal T_34 : std_logic;
  signal T_35 : std_logic;
  signal T_36 : std_logic;
  signal T_37 : std_logic;
  signal T_38 : std_logic;
  signal T_39 : std_logic;
  signal T_40 : std_logic;
  signal T_41 : std_logic;
  signal T_42 : std_logic;
  signal T_43 : std_logic;
  signal T_44 : std_logic;
  signal T_45 : std_logic;
  signal T_46 : std_logic;
  signal T_47 : std_logic;
  signal T_48 : std_logic;
  signal T_49 : std_logic;
  signal GATE_data_p2_0_LH_A : std_logic;
  signal GATE_data_p7_0_LH_A : std_logic;
  signal GATE_data_p8_6_LH_A : std_logic;
  signal GATE_T_5_A : std_logic;
  signal GATE_T_5_B : std_logic;
  signal GATE_T_6_A : std_logic;
  signal GATE_T_7_A : std_logic;
  signal GATE_T_7_B : std_logic;
  signal GATE_T_8_A : std_logic;
  signal GATE_T_9_A : std_logic;
  signal GATE_T_9_B : std_logic;
  signal GATE_T_10_A : std_logic;
  signal GATE_T_11_A : std_logic;
  signal GATE_T_11_B : std_logic;
  signal GATE_T_12_A : std_logic;
  signal GATE_T_13_A : std_logic;
  signal GATE_T_13_B : std_logic;
  signal GATE_T_17_A : std_logic;
  signal GATE_T_17_B : std_logic;
  signal GATE_T_19_A : std_logic;
  signal GATE_T_19_B : std_logic;
  signal GATE_T_20_A : std_logic;
  signal GATE_T_20_B : std_logic;
  signal GATE_T_21_A : std_logic;
  signal GATE_T_21_B : std_logic;
  signal GATE_T_23_A : std_logic;
  signal GATE_T_23_B : std_logic;
  signal GATE_T_24_A : std_logic;
  signal GATE_T_24_B : std_logic;
  signal GATE_T_25_A : std_logic;
  signal GATE_T_25_B : std_logic;
  signal GATE_T_26_A : std_logic;
  signal GATE_T_26_B : std_logic;
  signal GATE_T_27_A : std_logic;
  signal GATE_T_27_B : std_logic;
  signal GATE_T_29_A : std_logic;
  signal GATE_T_30_A : std_logic;
  signal GATE_T_33_A : std_logic;
  signal GATE_T_34_A : std_logic;
  signal GATE_T_37_A : std_logic;
  signal GATE_T_37_B : std_logic;
  signal GATE_T_38_A : std_logic;
  signal GATE_T_38_B : std_logic;
  signal GATE_T_40_A : std_logic;
  signal GATE_T_40_B : std_logic;
  signal GATE_T_41_A : std_logic;
  signal GATE_T_41_B : std_logic;
  signal GATE_T_43_A : std_logic;
  signal GATE_T_45_A : std_logic;
  signal GATE_T_47_A : std_logic;