output_pld.vm

TQ公司的STK16x开发系统的源码

//
// Written by Synplify
// Synplify Lite 7.1, Build 144R.
// Wed May 28 07:15:04 2003
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\c:\programme\isptools\synpbase\lib\vhd\std.vhd "
// file 2 "\w:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd "
// file 3 "\c:\programme\isptools\synpbase\lib\vhd\std1164.vhd "

`timescale 100 ps/100 ps
module IBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* IBUF */

module BI_DIR (
  O,
  I0,
  IO,
  OE
);
output O;
input I0;
inout IO;
input OE;
wire O ;
wire I0 ;
wire IO ;
wire OE ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  IO = OE ? I0 : 1'bz;
  assign #(1)  O = IO;
endmodule /* BI_DIR */

module OBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* OBUF */

module INV (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = ~ I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* INV */

module AND2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  & I1 ;
endmodule /* AND2 */

module MACH_LATCH (
  Q,
  D,
  LAT,
  R,
  S,
  NOTIFIER
);
output Q;
input D;
input LAT;
input R;
input S;
input NOTIFIER;
wire Q ;
wire D ;
wire LAT ;
wire R ;
wire S ;
wire NOTIFIER ;
wire un0 ;
wire un1 ;
wire true ;
wire false ;
  assign #(1)  un0 = ~ S;
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1) Q = un1 ? 1'b0 : (un0 ? 1'b1 : (LAT ? D : Q )); // latrs
endmodule /* MACH_LATCH */

module DLAT (
  Q,
  D,
  LAT
);
output Q;
input D;
input LAT;
wire Q ;
wire D ;
wire LAT ;
wire un0 ;
wire true ;
wire notifier ;
wire false ;
  MACH_LATCH INS4 (
	.Q(un0),
	.D(D),
	.LAT(LAT),
	.R(true),
	.S(true),
	.NOTIFIER(notifier)
);
  assign true = 1'b1;
  assign false = 1'b0;
  assign notifier = 1'b0;
assign Q = un0;
endmodule /* DLAT */

module OR2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  | I1 ;
endmodule /* OR2 */

module DLATRH (
  Q,
  D,
  LAT,
  R
);
output Q;
input D;
input LAT;
input R;
wire Q ;
wire D ;
wire LAT ;
wire R ;
wire un0 ;
wire un1 ;
wire true ;
wire notifier ;
wire false ;
  MACH_LATCH INS5 (
	.Q(un0),
	.D(D),
	.LAT(LAT),
	.R(un1),
	.S(true),
	.NOTIFIER(notifier)
);
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  assign notifier = 1'b0;
assign Q = un0;
endmodule /* DLATRH */

module Output_PLD (
  adresse,
  reset,
  rd,
  wr,
  cs,
  data,
  p2,
  p7,
  p8
);
input [5:0] adresse;
input reset;
input rd;
input wr;
input cs;
inout [7:0] data;
output [7:0] p2;
output [3:0] p7;
output [7:6] p8;
wire [5:0] adresse;
wire reset ;
wire rd ;
wire wr ;
wire cs ;
wire [7:0] data;
wire [7:0] p2;
wire [3:0] p7;
wire [7:6] p8;
wire [7:0] data_1;
wire [3:0] data_p7;
wire [7:0] data_p2;
wire [7:6] data_p8;
wire [7:6] un1_data_p2;
wire [7:0] data_p2_1;
wire [5:0] adresse_c;
wire [7:0] data_c;
wire [7:0] p2_c;
wire [3:0] p7_c;
wire [7:6] p8_c;
wire [5:0] adresse_c_i;
wire un1_un1_data_p821 ;
wire N_1 ;
wire N_3 ;
wire N_5 ;
wire N_7 ;
wire N_83 ;
wire N_84 ;
wire N_87 ;
wire N_88 ;
wire N_89 ;
wire N_90 ;
wire N_91 ;
wire N_92 ;
wire N_93 ;
wire N_94 ;
wire N_95 ;
wire N_99 ;
wire N_101 ;
wire N_103 ;
wire N_104 ;
wire \Port_sel.un109_data  ;
wire \Port_sel.un1_data_p821  ;
wire reset_c ;
wire rd_c ;
wire wr_c ;
wire cs_c ;
wire N_105 ;
wire N_106 ;
wire N_107 ;
wire N_108 ;
wire N_118 ;
wire N_119 ;
wire N_120 ;
wire N_121 ;
wire N_122 ;
wire N_123 ;
wire N_124 ;
wire N_125 ;
wire N_126 ;
wire rd_c_i ;
wire cs_c_i ;
wire wr_c_i ;
wire N_105_i ;
wire N_89_i ;
wire N_88_i ;
wire N_87_i ;
wire N_107_i ;
wire N_106_i ;
wire N_108_i ;
wire \Port_sel.un109_data_i  ;
wire reset_c_i ;
wire \un1_data_p2_1_0_0_.un3  ;
wire \un1_data_p2_1_0_0_.un1  ;
wire \un1_data_p2_1_0_0_.un0  ;
wire \un1_data_p2_1_0_1_.un3  ;
wire \un1_data_p2_1_0_1_.un1  ;
wire \un1_data_p2_1_0_1_.un0  ;
wire \un1_data_p2_1_0_2_.un3  ;
wire \un1_data_p2_1_0_2_.un1  ;
wire \un1_data_p2_1_0_2_.un0  ;
wire \un1_data_p2_1_0_3_.un3  ;
wire \un1_data_p2_1_0_3_.un1  ;
wire \un1_data_p2_1_0_3_.un0  ;
wire \un1_data_p2_2_0_6_.un3  ;
wire \un1_data_p2_2_0_6_.un1  ;
wire \un1_data_p2_2_0_6_.un0  ;
wire \un1_data_p2_2_0_7_.un3  ;
wire \un1_data_p2_2_0_7_.un1  ;
wire \un1_data_p2_2_0_7_.un0  ;
wire GND ;
wire VCC ;
  IBUF \adresse_Z[0]  (
	.O(adresse_c[0]),
	.I0(adresse[0])
);
  IBUF \adresse_Z[1]  (
	.O(adresse_c[1]),
	.I0(adresse[1])
);
  IBUF \adresse_Z[2]  (
	.O(adresse_c[2]),
	.I0(adresse[2])
);
  IBUF \adresse_Z[3]  (
	.O(adresse_c[3]),
	.I0(adresse[3])
);
  IBUF \adresse_Z[4]  (
	.O(adresse_c[4]),
	.I0(adresse[4])
);
  IBUF \adresse_Z[5]  (
	.O(adresse_c[5]),
	.I0(adresse[5])
);
  IBUF reset_Z (
	.O(reset_c),
	.I0(reset)
);
  IBUF rd_Z (
	.O(rd_c),
	.I0(rd)
);
  IBUF wr_Z (
	.O(wr_c),
	.I0(wr)
);
  IBUF cs_Z (
	.O(cs_c),
	.I0(cs)
);
  BI_DIR \data_Z[0]  (
	.O(data_c[0]),
	.I0(data_1[0]),
	.IO(data[0]),
	.OE(un1_un1_data_p821)
);
  BI_DIR \data_Z[1]  (
	.O(data_c[1]),
	.I0(data_1[1]),
	.IO(data[1]),
	.OE(un1_un1_data_p821)
);
  BI_DIR \data_Z[2]  (
	.O(data_c[2]),
	.I0(data_1[2]),
	.IO(data[2]),
	.OE(un1_un1_data_p821)
);
  BI_DIR \data_Z[3]  (
	.O(data_c[3]),
	.I0(data_1[3]),
	.IO(data[3]),
	.OE(un1_un1_data_p821)
);
  BI_DIR \data_Z[4]  (
	.O(data_c[4]),
	.I0(data_1[4]),
	.IO(data[4]),
	.OE(un1_un1_data_p821)
);
  BI_DIR \data_Z[5]  (
	.O(data_c[5]),
	.I0(data_1[5]),
	.IO(data[5]),
	.OE(un1_un1_data_p821)
);
  BI_DIR \data_Z[6]  (
	.O(data_c[6]),
	.I0(data_1[6]),
	.IO(data[6]),
	.OE(un1_un1_data_p821)
);
  BI_DIR \data_Z[7]  (
	.O(data_c[7]),
	.I0(data_1[7]),
	.IO(data[7]),
	.OE(un1_un1_data_p821)
);
  OBUF \p2_Z[0]  (
	.O(p2[0]),
	.I0(p2_c[0])
);
  OBUF \p2_Z[1]  (
	.O(p2[1]),
	.I0(p2_c[1])
);
  OBUF \p2_Z[2]  (
	.O(p2[2]),
	.I0(p2_c[2])
);
  OBUF \p2_Z[3]  (
	.O(p2[3]),
	.I0(p2_c[3])
);
  OBUF \p2_Z[4]  (
	.O(p2[4]),
	.I0(p2_c[4])
);
  OBUF \p2_Z[5]  (
	.O(p2[5]),
	.I0(p2_c[5])
);
  OBUF \p2_Z[6]  (
	.O(p2[6]),
	.I0(p2_c[6])
);
  OBUF \p2_Z[7]  (
	.O(p2[7]),
	.I0(p2_c[7])
);
  OBUF \p7_Z[0]  (
	.O(p7[0]),
	.I0(p7_c[0])
);
  OBUF \p7_Z[1]  (
	.O(p7[1]),
	.I0(p7_c[1])
);
  OBUF \p7_Z[2]  (
	.O(p7[2]),
	.I0(p7_c[2])
);
  OBUF \p7_Z[3]  (
	.O(p7[3]),
	.I0(p7_c[3])
);
  OBUF \p8_Z[6]  (
	.O(p8[6]),
	.I0(p8_c[6])
);
  OBUF \p8_Z[7]  (
	.O(p8[7]),
	.I0(p8_c[7])
);
  INV \adresse_c_i_Z[0]  (
	.O(adresse_c_i[0]),
	.I0(adresse_c[0])
);
  INV N_105_i_Z (
	.O(N_105_i),
	.I0(N_105)
);
  INV N_89_i_Z (
	.O(N_89_i),
	.I0(N_89)
);
  INV N_88_i_Z (
	.O(N_88_i),
	.I0(N_88)
);
  INV N_87_i_Z (
	.O(N_87_i),
	.I0(N_87)
);
  INV N_107_i_Z (
	.O(N_107_i),
	.I0(N_107)
);
  INV N_106_i_Z (
	.O(N_106_i),
	.I0(N_106)
);
  INV N_108_i_Z (
	.O(N_108_i),
	.I0(N_108)
);
  INV \Port_sel.un109_data_i_Z  (
	.O(\Port_sel.un109_data_i ),
	.I0(\Port_sel.un109_data )
);
  INV reset_c_i_Z (
	.O(reset_c_i),
	.I0(reset_c)
);
  AND2 un1_reset_1_i_0_and2_71 (
	.O(N_119),
	.I0(adresse_c_i[1]),
	.I1(adresse_c[0])
);
  AND2 G_47_72 (
	.O(N_120),
	.I0(wr_c_i),
	.I1(rd_c)
);
  AND2 G_45_73 (
	.O(N_121),
	.I0(adresse_c[3]),