output.tlg

来自「TQ公司的STK16x开发系统的源码」· TLG 代码 · 共 35 行

// Batch Timer Log File (Release Version: 2.01.28.41.02)

//  Project = output
//  Family  = mach4a
//  Device  = mach468a
//  Speed   = -5.5
//  Voltage = 5.0
//  Operating Condition = COM
//  Data sheet version  = RevD-8/2000

//  Pass Bidirection = OFF
//  Pass S/R = OFF
//  Pass Latch = OFF
//  Pass Clock = OFF
//  Maximum Paths = 20
//  T_SU Endpoints D/T inputs = ON
//  T_SU Endpoints CE inputs = OFF
//  T_SU Endpoints S/R inputs = OFF
//  T_SU Endpoints RAM gated = ON
//  Fmax of CE = ON
//  Fmax of RAM = ON

//  Location(From => To)
//    Pin number: numeric number preceded by "p", BGA number as is
//    Macrocell number: Segment#,GLB#,Macrocell#
//                      Segment#: starts from 0 (if applicable)
//                      GLB#: starts from A..Z, AA..ZZ
//                      Macrocell#: starts from 0 to 31

//  Register-to-register critical path delay: 9.0 ns
//    -     6.0  tGOAi                             data_p2_4.LH             ==>  data_p2_4.Q
//    -     0.0                                    data_p2_4.Q              ==>  data_4_.D
//    -     3.0  tSAL                              data_4_.D                ==>  data_4_.LH