output.lco

TQ公司的STK16x开发系统的源码

[DEVICE]
Family = M4A5;
PartType = M4A5-64/32;
Package = 48TQFP;
PartNumber = M4A5-64/32-55VC48;
Speed = -5.5;
Operating_condition = COM;
EN_Segment = No;
Pin_MC_1to1 = No;
EN_PinReserve_IO = Yes;
EN_PinReserve_BIDIR = Yes;
Voltage = 5.0;

[REVISION]
RCS = $Revision: 1.5 $;
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = output.tt4;
DATE = 5/28/03;
TIME = 08:15:12;
Source_Format = Schematic_VHDL;
Type = TT2;
Pre_Fit_Time = 1;

[IGNORE ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;

[CLEAR ASSIGNMENTS]
Pin_Assignments = No;
Pin_Keep_Block = No;
Pin_Keep_Segment = No;
Group_Assignments = No;
Macrocell_Assignments = No;
Macrocell_Keep_Block = No;
Macrocell_Keep_Segment = No;
Pin_Reservation = No;
Block_Reservation = No;
Segment_Reservation = No;
Timing_Constraints = No;

[BACKANNOTATE ASSIGNMENTS]
Pin_Block = No;
Pin_Macrocell_Block = No;
Routing = No;

[GLOBAL CONSTRAINTS]
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_GLB_Input_Percent = 100;
Max_Seg_In_Percent = 100;
Logic_Reduction = Yes;
XOR_Synthesis = Yes;
DT_Synthesis = Yes;
Netlist = VHDL;
Node_Collapse = Yes;
Run_Time = 0;
Set_Reset_Dont_Care = No;
Clock_Optimize = No;
In_Reg_Optimize = Yes;
Balanced_Partitioning = Yes;
Device_max_fanin = 33;
Device_max_pterms = 20;
Usercode = 0;
Usercode_Format = Hex;

[LOCATION ASSIGNMENTS]
layer = OFF;
adresse_5_ = pin, 27, -, C, -;
p2_7_ = pin, 3, -, A, -;
p7_3_ = pin, 12, -, B, -;
p8_7_ = pin, 14, -, B, -;
reset = pin, 29, -, -, -;
rd = pin, 20, -, C, -;
wr = pin, 21, -, C, -;
cs = pin, 16, -, B, -;
adresse_4_ = pin, 26, -, C, -;
adresse_3_ = pin, 25, -, C, -;
adresse_2_ = pin, 24, -, C, -;
adresse_1_ = pin, 23, -, C, -;
adresse_0_ = pin, 22, -, C, -;
p2_6_ = pin, 2, -, A, -;
p2_5_ = pin, 1, -, A, -;
p2_4_ = pin, 48, -, A, -;
p2_3_ = pin, 47, -, A, -;
p2_2_ = pin, 46, -, A, -;
p2_1_ = pin, 45, -, A, -;
p2_0_ = pin, 44, -, A, -;
p7_2_ = pin, 11, -, B, -;
p7_1_ = pin, 10, -, B, -;
p7_0_ = pin, 9, -, B, -;
p8_6_ = pin, 13, -, B, -;
data_7_ = pin, 40, -, D, -;
data_6_ = pin, 39, -, D, -;
data_5_ = pin, 38, -, D, -;
data_4_ = pin, 37, -, D, -;
data_3_ = pin, 36, -, D, -;
data_2_ = pin, 35, -, D, -;
data_1_ = pin, 34, -, D, -;
data_0_ = pin, 33, -, D, -;
un1_un1_data_p821 = node, -, -, B, 6;
data_p7_0 = node, -, -, C, 6;
data_p7_1 = node, -, -, C, 2;
data_p7_2 = node, -, -, C, 13;
data_p7_3 = node, -, -, C, 9;
data_p2_0 = node, -, -, C, 5;
data_p2_1 = node, -, -, C, 1;
data_p2_2 = node, -, -, B, 13;
data_p2_3 = node, -, -, C, 12;
data_p2_4 = node, -, -, C, 8;
data_p2_5 = node, -, -, C, 4;
data_p2_6 = node, -, -, C, 0;
data_p2_7 = node, -, -, A, 10;
data_p8_6 = node, -, -, A, 2;
data_p8_7 = node, -, -, A, 13;
N_106_iZ0 = node, -, -, D, 13;
N_108_iZ0 = node, -, -, B, 2;
Port_sel_un109_data_iZ0 = node, -, -, B, 9;
data_p8_6_0 = node, -, -, D, 6;

[GROUP ASSIGNMENTS]
layer = OFF;

[RESOURCE RESERVATIONS]
layer = OFF;

[SLEWRATE]
Default = FAST;

[PULLUP]
Default = Hold;

[NETLIST/DELAY FORMAT]
Delay_File = SDF;
Netlist = VHDL;

[OSM BYPASS]

[FITTER REPORT FORMAT]
Fitter_Options = Yes;
Pinout_Diagram = No;
Pinout_Listing = Yes;
Detailed_Block_Segment_Summary = Yes;
Input_Signal_List = Yes;
Output_Signal_List = Yes;
Bidir_Signal_List = Yes;
Node_Signal_List = Yes;
Signal_Fanout_List = Yes;
Block_Segment_Fanin_List = Yes;
Postfit_Eqn = Yes;
Prefit_Eqn = Yes;
Page_Break = Yes;

[POWER]
Powerlevel = Low, High;
Default = High;
Type = GLB;

[SOURCE CONSTRAINT OPTION]

[TIMING ANALYZER]
Last_source = ;Last_source_type = Fmax;

[Pin attributes list]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[global constraints list]

[Global Constraints Process Update]

[Explorer Results]

[Explorer User Settings]

[Timing Results]
Fmax = 111.11;
Logic_level = 1;