output.syn

TQ公司的STK16x开发系统的源码

JDF B
// Created by Version 2.1 
PROJECT Untitled
DESIGN tqs Normal
DEVKIT M4A5-64/32-55VC48
ENTRY Schematic/VHDL
MODULE output.vhd
MODSTYLE Output_PLD Normal
SYNTHESIS_TOOL Synplify