test_pld_1.srr

TQ公司的STK16x开发系统的源码

$ Start of Compile
#Tue May 27 09:38:33 2003

Synplicity VHDL Compiler, version 7.1, Build 158R, built Apr 18 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!
Synthesizing work.test_pld.ein_einfacher_test
Post processing for work.test_pld.ein_einfacher_test
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of dir_p2, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal dir_p2(7 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of NoName, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal data(0), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal data(1), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal data(2), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal data(3), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal data(4), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal data(5), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal data(6), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":31:0:31:3|Latch generated from process for signal data(7), probably caused by a missing assignment in an if or case stmt
@END
Process took 0.141 seconds realtime, 0.14 seconds cputime
Synplicity CPLD Technology Mapper, version 7.1, Build 144R, built Mar 28 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p8_4[7] on net p8[7] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p8_4[6] on net p8[6] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p7_4[3] on net p7[3] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p7_4[2] on net p7[2] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p7_4[1] on net p7[1] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p7_4[0] on net p7[0] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p2_4[7] on net p2[7] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p2_4[6] on net p2[6] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p2_4[5] on net p2[5] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p2_4[4] on net p2[4] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p2_4[3] on net p2[3] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p2_4[2] on net p2[2] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p2_4[1] on net p2[1] has its enable tied to GND (module Test_PLD) 
@W:"h:\tmp\lattice\tqs_1\tqs\test_pld_1.vhd":31:0:31:3|tristate driver p2_4[0] on net p2[0] has its enable tied to GND (module Test_PLD) 
---------------------------------------
Resource Usage Report

Simple gate primitives:
IBUF            10 uses
BI_DIR          22 uses
INV             48 uses
AND2            81 uses
DLAT            17 uses


Writing encrypted edif
Mapper successful!
Process took 0.266 seconds realtime, 0.281 seconds cputime