output_pld.vhm

TQ公司的STK16x开发系统的源码

      O => p2(3),
      I0 => P2_C(3));
  \II_P2[4]\: OBUF port map (
      O => p2(4),
      I0 => P2_C(4));
  \II_P2[5]\: OBUF port map (
      O => p2(5),
      I0 => P2_C(5));
  \II_P2[6]\: OBUF port map (
      O => p2(6),
      I0 => P2_C(6));
  \II_P2[7]\: OBUF port map (
      O => p2(7),
      I0 => P2_C(7));
  \II_P7[0]\: OBUF port map (
      O => p7(0),
      I0 => P7_C(0));
  \II_P7[1]\: OBUF port map (
      O => p7(1),
      I0 => P7_C(1));
  \II_P7[2]\: OBUF port map (
      O => p7(2),
      I0 => P7_C(2));
  \II_P7[3]\: OBUF port map (
      O => p7(3),
      I0 => P7_C(3));
  \II_P8[6]\: OBUF port map (
      O => p8(6),
      I0 => P8_C(6));
  \II_P8[7]\: OBUF port map (
      O => p8(7),
      I0 => P8_C(7));
  \II_ADRESSE_C_I[0]\: INV port map (
      O => ADRESSE_C_I(0),
      I0 => ADRESSE_C(0));
  II_N_105_I: INV port map (
      O => N_105_I,
      I0 => N_105);
  II_N_89_I: INV port map (
      O => N_89_I,
      I0 => N_89);
  II_N_88_I: INV port map (
      O => N_88_I,
      I0 => N_88);
  II_N_87_I: INV port map (
      O => N_87_I,
      I0 => N_87);
  II_N_107_I: INV port map (
      O => N_107_I,
      I0 => N_107);
  II_N_106_I: INV port map (
      O => N_106_I,
      I0 => N_106);
  II_N_108_I: INV port map (
      O => N_108_I,
      I0 => N_108);
  \II_PORT_SEL.UN109_DATA_I\: INV port map (
      O => \PORT_SEL.UN109_DATA_I\,
      I0 => \PORT_SEL.UN109_DATA\);
  II_RESET_C_I: INV port map (
      O => RESET_C_I,
      I0 => RESET_C);
  II_UN1_RESET_1_I_0_AND2_71: AND2 port map (
      O => N_119,
      I0 => ADRESSE_C_I(1),
      I1 => ADRESSE_C(0));
  II_G_47_72: AND2 port map (
      O => N_120,
      I0 => WR_C_I,
      I1 => RD_C);
  II_G_45_73: AND2 port map (
      O => N_121,
      I0 => ADRESSE_C(3),
      I1 => ADRESSE_C_I(4));
  II_G_45_74: AND2 port map (
      O => N_122,
      I0 => ADRESSE_C_I(2),
      I1 => CS_C_I);
  II_G_45_75: AND2 port map (
      O => N_123,
      I0 => ADRESSE_C_I(5),
      I1 => N_122);
  II_G_50_76: AND2 port map (
      O => N_124,
      I0 => WR_C,
      I1 => RD_C_I);
  II_UN1_DATA_P2_0_AND2_5_77: AND2 port map (
      O => N_125,
      I0 => DATA_P2(5),
      I1 => N_103);
  II_UN1_DATA_P2_0_AND2_4_78: AND2 port map (
      O => N_126,
      I0 => DATA_P2(4),
      I1 => N_103);
  II_RD_C_I: INV port map (
      O => RD_C_I,
      I0 => RD_C);
  \II_ADRESSE_C_I[5]\: INV port map (
      O => ADRESSE_C_I(5),
      I0 => ADRESSE_C(5));
  \II_ADRESSE_C_I[2]\: INV port map (
      O => ADRESSE_C_I(2),
      I0 => ADRESSE_C(2));
  II_CS_C_I: INV port map (
      O => CS_C_I,
      I0 => CS_C);
  \II_ADRESSE_C_I[4]\: INV port map (
      O => ADRESSE_C_I(4),
      I0 => ADRESSE_C(4));
  II_WR_C_I: INV port map (
      O => WR_C_I,
      I0 => WR_C);
  \II_ADRESSE_C_I[1]\: INV port map (
      O => ADRESSE_C_I(1),
      I0 => ADRESSE_C(1));
  II_G_45: AND2 port map (
      O => N_99,
      I0 => N_121,
      I1 => N_123);
  II_G_47: AND2 port map (
      O => N_101,
      I0 => N_99,
      I1 => N_120);
  II_G_50: AND2 port map (
      O => N_104,
      I0 => N_99,
      I1 => N_124);
  II_UN1_RESET_2_I_0_AND2: AND2 port map (
      O => N_88,
      I0 => N_101,
      I1 => N_118);
  II_UN1_RESET_1_I_0_AND2: AND2 port map (
      O => N_87,
      I0 => N_101,
      I1 => N_119);
  \II_UN1_DATA_P2_0_AND2[5]\: AND2 port map (
      O => N_84,
      I0 => N_104,
      I1 => N_125);
  \II_UN1_DATA_P2_0_AND2[4]\: AND2 port map (
      O => N_83,
      I0 => N_104,
      I1 => N_126);
  II_UN1_RESET_2_I_0_AND2_70: AND2 port map (
      O => N_118,
      I0 => ADRESSE_C_I(0),
      I1 => ADRESSE_C(1));
  \II_UN1_DATA_P2_2_0_0_AND2[1]\: AND2 port map (
      O => N_91,
      I0 => N_3,
      I1 => ADRESSE_C_I(1));
  \II_UN1_DATA_P2_2_0_0_AND2[2]\: AND2 port map (
      O => N_92,
      I0 => N_5,
      I1 => ADRESSE_C_I(1));
  \II_UN1_DATA_P2_2_0_0_AND2[3]\: AND2 port map (
      O => N_93,
      I0 => N_7,
      I1 => ADRESSE_C_I(1));
  \II_UN1_DATA_P2_1_0_0_AND2[6]\: AND2 port map (
      O => N_94,
      I0 => ADRESSE_C_I(0),
      I1 => DATA_P2(6));
  \II_UN1_DATA_P2_1_0_0_AND2[7]\: AND2 port map (
      O => N_95,
      I0 => ADRESSE_C_I(0),
      I1 => DATA_P2(7));
  \II_P7_0_AND2[3]\: AND2 port map (
      O => P7_C(3),
      I0 => DATA_P7(3),
      I1 => RESET_C);
  \II_P8_0_AND2[6]\: AND2 port map (
      O => P8_C(6),
      I0 => DATA_P8(6),
      I1 => RESET_C);
  \II_P8_0_AND2[7]\: AND2 port map (
      O => P8_C(7),
      I0 => DATA_P8(7),
      I1 => RESET_C);
  \II_DATA_P2_1_0_AND2[0]\: AND2 port map (
      O => DATA_P2_1(0),
      I0 => DATA_C(0),
      I1 => RESET_C);
  \II_DATA_P2_1_0_AND2[1]\: AND2 port map (
      O => DATA_P2_1(1),
      I0 => DATA_C(1),
      I1 => RESET_C);
  \II_DATA_P2_1_0_AND2[2]\: AND2 port map (
      O => DATA_P2_1(2),
      I0 => DATA_C(2),
      I1 => RESET_C);
  \II_DATA_P2_1_0_AND2[3]\: AND2 port map (
      O => DATA_P2_1(3),
      I0 => DATA_C(3),
      I1 => RESET_C);
  \II_DATA_P2_1_0_AND2[4]\: AND2 port map (
      O => DATA_P2_1(4),
      I0 => DATA_C(4),
      I1 => RESET_C);
  \II_DATA_P2_1_0_AND2[5]\: AND2 port map (
      O => DATA_P2_1(5),
      I0 => DATA_C(5),
      I1 => RESET_C);
  \II_DATA_P2_1_0_AND2[6]\: AND2 port map (
      O => DATA_P2_1(6),
      I0 => DATA_C(6),
      I1 => RESET_C);
  \II_DATA_P2_1_0_AND2[7]\: AND2 port map (
      O => DATA_P2_1(7),
      I0 => DATA_C(7),
      I1 => RESET_C);
  \II_PORT_SEL.UN1_DATA_P821_0_AND2\: AND2 port map (
      O => \PORT_SEL.UN1_DATA_P821\,
      I0 => N_104,
      I1 => N_105_I);
  \II_PORT_SEL.UN109_DATA_0_AND2\: AND2 port map (
      O => \PORT_SEL.UN109_DATA\,
      I0 => N_101,
      I1 => N_105_I);
  II_UN1_RESET_3_I_0_AND2: AND2 port map (
      O => N_89,
      I0 => N_101,
      I1 => N_103);
  \II_UN1_DATA_P2_2_0_0_AND2[0]\: AND2 port map (
      O => N_90,
      I0 => N_1,
      I1 => ADRESSE_C_I(1));
  II_UN1_RESET_1_I_0: AND2 port map (
      O => N_108,
      I0 => N_87_I,
      I1 => RESET_C);
  II_UN1_RESET_2_I_0: AND2 port map (
      O => N_107,
      I0 => N_88_I,
      I1 => RESET_C);
  II_UN1_RESET_3_I_0: AND2 port map (
      O => N_106,
      I0 => N_89_I,
      I1 => RESET_C);
  II_G_51: AND2 port map (
      O => N_105,
      I0 => ADRESSE_C(0),
      I1 => ADRESSE_C(1));
  \II_P2_0_AND2[0]\: AND2 port map (
      O => P2_C(0),
      I0 => DATA_P2(0),
      I1 => RESET_C);
  \II_P2_0_AND2[1]\: AND2 port map (
      O => P2_C(1),
      I0 => DATA_P2(1),
      I1 => RESET_C);
  \II_P2_0_AND2[2]\: AND2 port map (
      O => P2_C(2),
      I0 => DATA_P2(2),
      I1 => RESET_C);
  \II_P2_0_AND2[3]\: AND2 port map (
      O => P2_C(3),
      I0 => DATA_P2(3),
      I1 => RESET_C);
  \II_P2_0_AND2[4]\: AND2 port map (
      O => P2_C(4),
      I0 => DATA_P2(4),
      I1 => RESET_C);
  \II_P2_0_AND2[5]\: AND2 port map (
      O => P2_C(5),
      I0 => DATA_P2(5),
      I1 => RESET_C);
  \II_P2_0_AND2[6]\: AND2 port map (
      O => P2_C(6),
      I0 => DATA_P2(6),
      I1 => RESET_C);
  \II_P2_0_AND2[7]\: AND2 port map (
      O => P2_C(7),
      I0 => DATA_P2(7),
      I1 => RESET_C);
  \II_P7_0_AND2[0]\: AND2 port map (
      O => P7_C(0),
      I0 => DATA_P7(0),
      I1 => RESET_C);
  \II_P7_0_AND2[1]\: AND2 port map (
      O => P7_C(1),
      I0 => DATA_P7(1),
      I1 => RESET_C);
  \II_P7_0_AND2[2]\: AND2 port map (
      O => P7_C(2),
      I0 => DATA_P7(2),
      I1 => RESET_C);
  \II_DATA_P2[2]\: DLAT port map (
      Q => DATA_P2(2),
      D => DATA_P2_1(2),
      LAT => N_106_I);
  \II_DATA_P2[3]\: DLAT port map (
      Q => DATA_P2(3),
      D => DATA_P2_1(3),
      LAT => N_106_I);
  \II_DATA_P2[4]\: DLAT port map (
      Q => DATA_P2(4),
      D => DATA_P2_1(4),
      LAT => N_106_I);
  \II_DATA_P2[5]\: DLAT port map (
      Q => DATA_P2(5),
      D => DATA_P2_1(5),
      LAT => N_106_I);
  \II_DATA_P2[6]\: DLAT port map (
      Q => DATA_P2(6),
      D => DATA_P2_1(6),
      LAT => N_106_I);
  \II_DATA_P2[7]\: DLAT port map (
      Q => DATA_P2(7),
      D => DATA_P2_1(7),
      LAT => N_106_I);
  \II_DATA_P8[6]\: DLAT port map (
      Q => DATA_P8(6),
      D => DATA_P2_1(6),
      LAT => N_107_I);
  \II_DATA_P8[7]\: DLAT port map (
      Q => DATA_P8(7),
      D => DATA_P2_1(7),
      LAT => N_107_I);
  \II_UN1_DATA_P2_1_0_0_.R\: INV port map (
      O => \UN1_DATA_P2_1_0_0_.UN3\,
      I0 => ADRESSE_C(0));
  \II_UN1_DATA_P2_1_0_0_.M\: AND2 port map (
      O => \UN1_DATA_P2_1_0_0_.UN1\,
      I0 => DATA_P7(0),
      I1 => ADRESSE_C(0));
  \II_UN1_DATA_P2_1_0_0_.N\: AND2 port map (
      O => \UN1_DATA_P2_1_0_0_.UN0\,
      I0 => DATA_P2(0),
      I1 => \UN1_DATA_P2_1_0_0_.UN3\);
  \II_UN1_DATA_P2_1_0_0_.P\: OR2 port map (
      O => N_1,
      I0 => \UN1_DATA_P2_1_0_0_.UN1\,
      I1 => \UN1_DATA_P2_1_0_0_.UN0\);
  \II_UN1_DATA_P2_1_0_1_.R\: INV port map (
      O => \UN1_DATA_P2_1_0_1_.UN3\,
      I0 => ADRESSE_C(0));
  \II_UN1_DATA_P2_1_0_1_.M\: AND2 port map (
      O => \UN1_DATA_P2_1_0_1_.UN1\,
      I0 => DATA_P7(1),
      I1 => ADRESSE_C(0));
  \II_UN1_DATA_P2_1_0_1_.N\: AND2 port map (
      O => \UN1_DATA_P2_1_0_1_.UN0\,
      I0 => DATA_P2(1),
      I1 => \UN1_DATA_P2_1_0_1_.UN3\);
  \II_UN1_DATA_P2_1_0_1_.P\: OR2 port map (
      O => N_3,
      I0 => \UN1_DATA_P2_1_0_1_.UN1\,
      I1 => \UN1_DATA_P2_1_0_1_.UN0\);
  \II_UN1_DATA_P2_1_0_2_.R\: INV port map (
      O => \UN1_DATA_P2_1_0_2_.UN3\,
      I0 => ADRESSE_C(0));
  \II_UN1_DATA_P2_1_0_2_.M\: AND2 port map (
      O => \UN1_DATA_P2_1_0_2_.UN1\,
      I0 => DATA_P7(2),
      I1 => ADRESSE_C(0));
  \II_UN1_DATA_P2_1_0_2_.N\: AND2 port map (
      O => \UN1_DATA_P2_1_0_2_.UN0\,
      I0 => DATA_P2(2),
      I1 => \UN1_DATA_P2_1_0_2_.UN3\);
  \II_UN1_DATA_P2_1_0_2_.P\: OR2 port map (
      O => N_5,
      I0 => \UN1_DATA_P2_1_0_2_.UN1\,
      I1 => \UN1_DATA_P2_1_0_2_.UN0\);
  \II_UN1_DATA_P2_1_0_3_.R\: INV port map (
      O => \UN1_DATA_P2_1_0_3_.UN3\,
      I0 => ADRESSE_C(0));
  \II_UN1_DATA_P2_1_0_3_.M\: AND2 port map (
      O => \UN1_DATA_P2_1_0_3_.UN1\,
      I0 => DATA_P7(3),
      I1 => ADRESSE_C(0));
  \II_UN1_DATA_P2_1_0_3_.N\: AND2 port map (
      O => \UN1_DATA_P2_1_0_3_.UN0\,
      I0 => DATA_P2(3),
      I1 => \UN1_DATA_P2_1_0_3_.UN3\);
  \II_UN1_DATA_P2_1_0_3_.P\: OR2 port map (
      O => N_7,
      I0 => \UN1_DATA_P2_1_0_3_.UN1\,
      I1 => \UN1_DATA_P2_1_0_3_.UN0\);
  \II_UN1_DATA_P2_2_0_6_.R\: INV port map (
      O => \UN1_DATA_P2_2_0_6_.UN3\,
      I0 => ADRESSE_C(1));
  \II_UN1_DATA_P2_2_0_6_.M\: AND2 port map (
      O => \UN1_DATA_P2_2_0_6_.UN1\,
      I0 => DATA_P8(6),
      I1 => ADRESSE_C(1));
  \II_UN1_DATA_P2_2_0_6_.N\: AND2 port map (
      O => \UN1_DATA_P2_2_0_6_.UN0\,
      I0 => N_94,
      I1 => \UN1_DATA_P2_2_0_6_.UN3\);
  \II_UN1_DATA_P2_2_0_6_.P\: OR2 port map (
      O => UN1_DATA_P2(6),
      I0 => \UN1_DATA_P2_2_0_6_.UN1\,
      I1 => \UN1_DATA_P2_2_0_6_.UN0\);
  \II_UN1_DATA_P2_2_0_7_.R\: INV port map (
      O => \UN1_DATA_P2_2_0_7_.UN3\,
      I0 => ADRESSE_C(1));
  \II_UN1_DATA_P2_2_0_7_.M\: AND2 port map (
      O => \UN1_DATA_P2_2_0_7_.UN1\,
      I0 => DATA_P8(7),
      I1 => ADRESSE_C(1));
  \II_UN1_DATA_P2_2_0_7_.N\: AND2 port map (
      O => \UN1_DATA_P2_2_0_7_.UN0\,
      I0 => N_95,
      I1 => \UN1_DATA_P2_2_0_7_.UN3\);
  \II_UN1_DATA_P2_2_0_7_.P\: OR2 port map (
      O => UN1_DATA_P2(7),
      I0 => \UN1_DATA_P2_2_0_7_.UN1\,
      I1 => \UN1_DATA_P2_2_0_7_.UN0\);
  II_G_49: AND2 port map (
      O => N_103,
      I0 => ADRESSE_C_I(0),
      I1 => ADRESSE_C_I(1));
  II_UN1_UN1_DATA_P821: DLATRH port map (
      Q => UN1_UN1_DATA_P821,
      D => \PORT_SEL.UN1_DATA_P821\,
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_1[4]\: DLATRH port map (
      Q => DATA_1(4),
      D => N_83,
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_1[5]\: DLATRH port map (
      Q => DATA_1(5),
      D => N_84,
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_1[0]\: DLATRH port map (
      Q => DATA_1(0),
      D => N_90,
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_1[1]\: DLATRH port map (
      Q => DATA_1(1),
      D => N_91,
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_1[2]\: DLATRH port map (
      Q => DATA_1(2),
      D => N_92,
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_1[3]\: DLATRH port map (
      Q => DATA_1(3),
      D => N_93,
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_1[6]\: DLATRH port map (
      Q => DATA_1(6),
      D => UN1_DATA_P2(6),
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_1[7]\: DLATRH port map (
      Q => DATA_1(7),
      D => UN1_DATA_P2(7),
      LAT => \PORT_SEL.UN109_DATA_I\,
      R => RESET_C_I);
  \II_DATA_P7[0]\: DLAT port map (
      Q => DATA_P7(0),
      D => DATA_P2_1(0),
      LAT => N_108_I);
  \II_DATA_P7[1]\: DLAT port map (
      Q => DATA_P7(1),
      D => DATA_P2_1(1),
      LAT => N_108_I);
  \II_DATA_P7[2]\: DLAT port map (
      Q => DATA_P7(2),
      D => DATA_P2_1(2),
      LAT => N_108_I);
  \II_DATA_P7[3]\: DLAT port map (
      Q => DATA_P7(3),
      D => DATA_P2_1(3),
      LAT => N_108_I);
  \II_DATA_P2[0]\: DLAT port map (
      Q => DATA_P2(0),
      D => DATA_P2_1(0),
      LAT => N_106_I);
  \II_DATA_P2[1]\: DLAT port map (
      Q => DATA_P2(1),
      D => DATA_P2_1(1),
      LAT => N_106_I);
  GND <= '0';
  VCC <= '1';
end beh;