output_pld.vhm

TQ公司的STK16x开发系统的源码

--
-- Written by Synplicity
-- Wed May 28 07:15:04 2003
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity MACH_LATCH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  LAT :  in std_logic;
  R :  in std_logic;
  S :  in std_logic;
  NOTIFIER :  in std_logic);
end MACH_LATCH;

architecture beh of MACH_LATCH is
  signal UN0 : std_logic ;
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  UN0 <= not S;
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  II_Q: prim_latch port map (Q, D, LAT, UN1, UN0);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity AND2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 and I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity BI_DIR is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  IO :  inout std_logic;
  OE :  in std_logic);
end BI_DIR;

architecture beh of BI_DIR is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  IO <= I0 after 100 ps when OE = '1' else 'Z' after 100 ps;
  O <= IO;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity DLAT is
port(
  Q :  out std_logic;
  D :  in std_logic;
  LAT :  in std_logic);
end DLAT;

architecture beh of DLAT is
  signal NN_1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_LATCH
    port(
      Q :  out std_logic;
      D :  in std_logic;
      LAT :  in std_logic;
      R :  in std_logic;
      S :  in std_logic;
      NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS4: MACH_LATCH port map (
      Q => Q,
      D => D,
      LAT => LAT,
      R => NN_1,
      S => NN_1,
      NOTIFIER => NOTIFIER);
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity DLATRH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  LAT :  in std_logic;
  R :  in std_logic);
end DLATRH;

architecture beh of DLATRH is
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_LATCH
    port(
      Q :  out std_logic;
      D :  in std_logic;
      LAT :  in std_logic;
      R :  in std_logic;
      S :  in std_logic;
      NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS5: MACH_LATCH port map (
      Q => Q,
      D => D,
      LAT => LAT,
      R => UN1,
      S => NN_1,
      NOTIFIER => NOTIFIER);
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity IBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity INV is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end INV;

architecture beh of INV is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= not I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end OBUF;

architecture beh of OBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OR2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end OR2;

architecture beh of OR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 or I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity Output_PLD is
port(
  adresse : in std_logic_vector(5 downto 0);
  reset :  in std_logic;
  rd :  in std_logic;
  wr :  in std_logic;
  cs :  in std_logic;
  data : inout std_logic_vector(7 downto 0);
  p2 : out std_logic_vector(7 downto 0);
  p7 : out std_logic_vector(3 downto 0);
  p8 : out std_logic_vector(7 downto 6));
end Output_PLD;

architecture beh of Output_PLD is
  signal DATA_1 : std_logic_vector(7 downto 0);
  signal DATA_P7 : std_logic_vector(3 downto 0);
  signal DATA_P2 : std_logic_vector(7 downto 0);
  signal DATA_P8 : std_logic_vector(7 downto 6);
  signal UN1_DATA_P2 : std_logic_vector(7 downto 6);
  signal DATA_P2_1 : std_logic_vector(7 downto 0);
  signal ADRESSE_C : std_logic_vector(5 downto 0);
  signal DATA_C : std_logic_vector(7 downto 0);
  signal P2_C : std_logic_vector(7 downto 0);
  signal P7_C : std_logic_vector(3 downto 0);
  signal P8_C : std_logic_vector(7 downto 6);
  signal ADRESSE_C_I : std_logic_vector(5 downto 0);
  signal UN1_UN1_DATA_P821 : std_logic ;
  signal N_1 : std_logic ;
  signal N_3 : std_logic ;
  signal N_5 : std_logic ;
  signal N_7 : std_logic ;
  signal N_83 : std_logic ;
  signal N_84 : std_logic ;
  signal N_87 : std_logic ;
  signal N_88 : std_logic ;
  signal N_89 : std_logic ;
  signal N_90 : std_logic ;
  signal N_91 : std_logic ;
  signal N_92 : std_logic ;
  signal N_93 : std_logic ;
  signal N_94 : std_logic ;
  signal N_95 : std_logic ;
  signal N_99 : std_logic ;
  signal N_101 : std_logic ;
  signal N_103 : std_logic ;
  signal N_104 : std_logic ;
  signal \PORT_SEL.UN109_DATA\ : std_logic ;
  signal \PORT_SEL.UN1_DATA_P821\ : std_logic ;
  signal RESET_C : std_logic ;
  signal RD_C : std_logic ;
  signal WR_C : std_logic ;
  signal CS_C : std_logic ;
  signal N_105 : std_logic ;
  signal N_106 : std_logic ;
  signal N_107 : std_logic ;
  signal N_108 : std_logic ;
  signal N_118 : std_logic ;
  signal N_119 : std_logic ;
  signal N_120 : std_logic ;
  signal N_121 : std_logic ;
  signal N_122 : std_logic ;
  signal N_123 : std_logic ;
  signal N_124 : std_logic ;
  signal N_125 : std_logic ;
  signal N_126 : std_logic ;
  signal RD_C_I : std_logic ;
  signal CS_C_I : std_logic ;
  signal WR_C_I : std_logic ;
  signal N_105_I : std_logic ;
  signal N_89_I : std_logic ;
  signal N_88_I : std_logic ;
  signal N_87_I : std_logic ;
  signal N_107_I : std_logic ;
  signal N_106_I : std_logic ;
  signal N_108_I : std_logic ;
  signal \PORT_SEL.UN109_DATA_I\ : std_logic ;
  signal RESET_C_I : std_logic ;
  signal \UN1_DATA_P2_1_0_0_.UN3\ : std_logic ;
  signal \UN1_DATA_P2_1_0_0_.UN1\ : std_logic ;
  signal \UN1_DATA_P2_1_0_0_.UN0\ : std_logic ;
  signal \UN1_DATA_P2_1_0_1_.UN3\ : std_logic ;
  signal \UN1_DATA_P2_1_0_1_.UN1\ : std_logic ;
  signal \UN1_DATA_P2_1_0_1_.UN0\ : std_logic ;
  signal \UN1_DATA_P2_1_0_2_.UN3\ : std_logic ;
  signal \UN1_DATA_P2_1_0_2_.UN1\ : std_logic ;
  signal \UN1_DATA_P2_1_0_2_.UN0\ : std_logic ;
  signal \UN1_DATA_P2_1_0_3_.UN3\ : std_logic ;
  signal \UN1_DATA_P2_1_0_3_.UN1\ : std_logic ;
  signal \UN1_DATA_P2_1_0_3_.UN0\ : std_logic ;
  signal \UN1_DATA_P2_2_0_6_.UN3\ : std_logic ;
  signal \UN1_DATA_P2_2_0_6_.UN1\ : std_logic ;
  signal \UN1_DATA_P2_2_0_6_.UN0\ : std_logic ;
  signal \UN1_DATA_P2_2_0_7_.UN3\ : std_logic ;
  signal \UN1_DATA_P2_2_0_7_.UN1\ : std_logic ;
  signal \UN1_DATA_P2_2_0_7_.UN0\ : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component IBUF
    port(
      O :  out std_logic;
      I0 :  in std_logic  );
  end component;
  component BI_DIR
    port(
      O :  out std_logic;
      I0 :  in std_logic;
      IO :  inout std_logic;
      OE :  in std_logic  );
  end component;
  component OBUF
    port(
      O :  out std_logic;
      I0 :  in std_logic  );
  end component;
  component INV
    port(
      O :  out std_logic;
      I0 :  in std_logic  );
  end component;
  component AND2
    port(
      O :  out std_logic;
      I0 :  in std_logic;
      I1 :  in std_logic  );
  end component;
  component DLAT
    port(
      Q :  out std_logic;
      D :  in std_logic;
      LAT :  in std_logic  );
  end component;
  component OR2
    port(
      O :  out std_logic;
      I0 :  in std_logic;
      I1 :  in std_logic  );
  end component;
  component DLATRH
    port(
      Q :  out std_logic;
      D :  in std_logic;
      LAT :  in std_logic;
      R :  in std_logic  );
  end component;
begin
  \II_ADRESSE[0]\: IBUF port map (
      O => ADRESSE_C(0),
      I0 => adresse(0));
  \II_ADRESSE[1]\: IBUF port map (
      O => ADRESSE_C(1),
      I0 => adresse(1));
  \II_ADRESSE[2]\: IBUF port map (
      O => ADRESSE_C(2),
      I0 => adresse(2));
  \II_ADRESSE[3]\: IBUF port map (
      O => ADRESSE_C(3),
      I0 => adresse(3));
  \II_ADRESSE[4]\: IBUF port map (
      O => ADRESSE_C(4),
      I0 => adresse(4));
  \II_ADRESSE[5]\: IBUF port map (
      O => ADRESSE_C(5),
      I0 => adresse(5));
  II_RESET: IBUF port map (
      O => RESET_C,
      I0 => reset);
  II_RD: IBUF port map (
      O => RD_C,
      I0 => rd);
  II_WR: IBUF port map (
      O => WR_C,
      I0 => wr);
  II_CS: IBUF port map (
      O => CS_C,
      I0 => cs);
  \II_DATA[0]\: BI_DIR port map (
      O => DATA_C(0),
      I0 => DATA_1(0),
      IO => data(0),
      OE => UN1_UN1_DATA_P821);
  \II_DATA[1]\: BI_DIR port map (
      O => DATA_C(1),
      I0 => DATA_1(1),
      IO => data(1),
      OE => UN1_UN1_DATA_P821);
  \II_DATA[2]\: BI_DIR port map (
      O => DATA_C(2),
      I0 => DATA_1(2),
      IO => data(2),
      OE => UN1_UN1_DATA_P821);
  \II_DATA[3]\: BI_DIR port map (
      O => DATA_C(3),
      I0 => DATA_1(3),
      IO => data(3),
      OE => UN1_UN1_DATA_P821);
  \II_DATA[4]\: BI_DIR port map (
      O => DATA_C(4),
      I0 => DATA_1(4),
      IO => data(4),
      OE => UN1_UN1_DATA_P821);
  \II_DATA[5]\: BI_DIR port map (
      O => DATA_C(5),
      I0 => DATA_1(5),
      IO => data(5),
      OE => UN1_UN1_DATA_P821);
  \II_DATA[6]\: BI_DIR port map (
      O => DATA_C(6),
      I0 => DATA_1(6),
      IO => data(6),
      OE => UN1_UN1_DATA_P821);
  \II_DATA[7]\: BI_DIR port map (
      O => DATA_C(7),
      I0 => DATA_1(7),
      IO => data(7),
      OE => UN1_UN1_DATA_P821);
  \II_P2[0]\: OBUF port map (
      O => p2(0),
      I0 => P2_C(0));
  \II_P2[1]\: OBUF port map (
      O => p2(1),
      I0 => P2_C(1));
  \II_P2[2]\: OBUF port map (
      O => p2(2),
      I0 => P2_C(2));
  \II_P2[3]\: OBUF port map (