proj_1.prj

TQ公司的STK16x开发系统的源码

#-- Synplicity, Inc.
#-- Version 7.1        
#-- Project file H:\TMP\Lattice\TQS_1\TQS\proj_1.prj
#-- Written on Tue May 27 10:24:45 2003


#add_file options
add_file -vhdl -lib work "test_pld_1.vhd"

#reporting options


#implementation: "rev_2"
impl -add rev_2

#device options
set_option -technology MACH
set_option -part M4-64

#compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 0.000
set_option -fanin_limit 20
set_option -max_terms_per_macrocell 16
set_option -domap 0
set_option -area_delay_percent 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_2/test_pld_1.edf"

#implementation attributes
set_option -vlog_std v95
set_option -compiler_compatible 0
impl -active "rev_2"