output_pld.tlg

TQ公司的STK16x开发系统的源码

Synthesizing work.output_pld.output
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":29:10:29:16|Incomplete sensitivity list - assuming completeness
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:7:33:11|Referenced variable reset is not in sensitivity list
Post processing for work.output_pld.output
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data_p8, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data_p8(7 downto 6), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data_p2, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data_p2(7 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data_p7, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data_p7(3 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of NoName, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data(0), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data(1), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data(2), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data(3), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data(4), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data(5), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data(6), probably caused by a missing assignment in an if or case stmt
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"W:\projekte\tqmx16xu\rev100a\sw\pld\output\output.vhd":33:4:33:5|Latch generated from process for signal data(7), probably caused by a missing assignment in an if or case stmt