📄 output.prd
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===========================================================================
< Block [ 2] > Logic Array Fan-in
===========================================================================
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| IOPin 3 4 ( 37)| data_4_
Mux01| ... | ...
Mux02| ... | ...
Mux03| Mcel 3 13 ( 141)| N_106_iZ0
Mux04| ... | ...
Mux05| IOPin 3 1 ( 34)| data_1_
Mux06| Input Pin ( 29)| reset
Mux07| IOPin 3 0 ( 33)| data_0_
Mux08| Mcel 1 2 ( 76)| N_108_iZ0
Mux09| ... | ...
Mux10| ... | ...
Mux11| ... | ...
Mux12| ... | ...
Mux13| IOPin 3 2 ( 35)| data_2_
Mux14| ... | ...
Mux15| ... | ...
Mux16| IOPin 3 6 ( 39)| data_6_
Mux17| IOPin 3 3 ( 36)| data_3_
Mux18| ... | ...
Mux19| ... | ...
Mux20| IOPin 3 5 ( 38)| data_5_
Mux21| ... | ...
Mux22| ... | ...
Mux23| ... | ...
Mux24| ... | ...
Mux25| ... | ...
Mux26| ... | ...
Mux27| ... | ...
Mux28| ... | ...
Mux29| ... | ...
Mux30| ... | ...
Mux31| ... | ...
Mux32| ... | ...
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| data_6_| IO| | A | 2 | 2 to [ 0]| 1 XOR free
1| data_7_| IO| | A | 2 | 2 to [ 1]| 1 XOR free
2| data_0_| IO| | A | 2 | 2 to [ 2]| 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| data_2_| IO| | A | 2 | 2 to [ 4]| 1 XOR free
5| data_1_| IO| | A | 2 | 2 to [ 5]| 1 XOR free
6| data_p8_6_0|NOD| | S | 2 | 4 to [ 6]| 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| data_3_| IO| | A | 2 | 2 to [ 8]| 1 XOR free
9| data_4_| IO| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| data_5_| IO| | A | 1 | 2 free | 1 XOR to [12] for 1 PT sig
13| N_106_iZ0|NOD| | S | 2 | 4 to [13]| 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| data_6_| IO| | A | 2 |=> can support up to [ 3] logic PT(s)
1| data_7_| IO| | A | 2 |=> can support up to [ 8] logic PT(s)
2| data_0_| IO| | A | 2 |=> can support up to [ 8] logic PT(s)
3| | ? | | S | |=> can support up to [ 5] logic PT(s)
4| data_2_| IO| | A | 2 |=> can support up to [ 8] logic PT(s)
5| data_1_| IO| | A | 2 |=> can support up to [ 8] logic PT(s)
6| data_p8_6_0|NOD| | S | 2 |=> can support up to [ 10] logic PT(s)
7| | ? | | S | |=> can support up to [ 7] logic PT(s)
8| data_3_| IO| | A | 2 |=> can support up to [ 15] logic PT(s)
9| data_4_| IO| | A | 1 |=> can support up to [ 13] logic PT(s)
10| | ? | | S | |=> can support up to [ 14] logic PT(s)
11| | ? | | S | |=> can support up to [ 12] logic PT(s)
12| data_5_| IO| | A | 1 |=> can support up to [ 13] logic PT(s)
13| N_106_iZ0|NOD| | S | 2 |=> can support up to [ 17] logic PT(s)
14| | ? | | S | |=> can support up to [ 10] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 3] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| data_6_| IO| | => | 5 ( 6) 7 0 | 38 ( 39) 40 33
1| data_7_| IO| | => | 5 6 ( 7) 0 | 38 39 ( 40) 33
2| data_0_| IO| | => | 6 7 ( 0) 1 | 39 40 ( 33) 34
3| | | | => | 6 7 0 1 | 39 40 33 34
4| data_2_| IO| | => | 7 0 1 ( 2)| 40 33 34 ( 35)
5| data_1_| IO| | => | 7 0 ( 1) 2 | 40 33 ( 34) 35
6| data_p8_6_0|NOD| | => | 0 1 2 3 | 33 34 35 36
7| | | | => | 0 1 2 3 | 33 34 35 36
8| data_3_| IO| | => | 1 2 ( 3) 4 | 34 35 ( 36) 37
9| data_4_| IO| | => | 1 2 3 ( 4)| 34 35 36 ( 37)
10| | | | => | 2 3 4 5 | 35 36 37 38
11| | | | => | 2 3 4 5 | 35 36 37 38
12| data_5_| IO| | => | 3 4 ( 5) 6 | 36 37 ( 38) 39
13| N_106_iZ0|NOD| | => | 3 4 5 6 | 36 37 38 39
14| | | | => | 4 5 6 7 | 37 38 39 40
15| | | | => | 4 5 6 7 | 37 38 39 40
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > IO-to-Node Pin Mapping
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| data_0_| IO|*| 33| => | 0 1 ( 2) 3 4 5 6 7
1| data_1_| IO|*| 34| => | 2 3 4 ( 5) 6 7 8 9
2| data_2_| IO|*| 35| => | ( 4) 5 6 7 8 9 10 11
3| data_3_| IO|*| 36| => | 6 7 ( 8) 9 10 11 12 13
4| data_4_| IO|*| 37| => | 8 ( 9) 10 11 12 13 14 15
5| data_5_| IO|*| 38| => | 10 11 (12) 13 14 15 0 1
6| data_6_| IO|*| 39| => | 12 13 14 15 ( 0) 1 2 3
7| data_7_| IO|*| 40| => | 14 15 0 ( 1) 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > IO/Node and IO/Input Macrocell Pairing Table
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| data_0_| IO|*| 33| => | Input macrocell [ -]
1| data_1_| IO|*| 34| => | Input macrocell [ -]
2| data_2_| IO|*| 35| => | Input macrocell [ -]
3| data_3_| IO|*| 36| => | Input macrocell [ -]
4| data_4_| IO|*| 37| => | Input macrocell [ -]
5| data_5_| IO|*| 38| => | Input macrocell [ -]
6| data_6_| IO|*| 39| => | Input macrocell [ -]
7| data_7_| IO|*| 40| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 33| IO data_0_|*|*]
[RegIn 0 |122| -| | ]
[MCell 0 |121| IO data_6_| | ]
[MCell 1 |123| IO data_7_| | ]
1 [IOpin 1 | 34| IO data_1_|*|*]
[RegIn 1 |125| -| | ]
[MCell 2 |124| IO data_0_| | ]
[MCell 3 |126| -| | ]
2 [IOpin 2 | 35| IO data_2_|*|*]
[RegIn 2 |128| -| | ]
[MCell 4 |127| IO data_2_| | ]
[MCell 5 |129| IO data_1_| | ]
3 [IOpin 3 | 36| IO data_3_|*|*]
[RegIn 3 |131| -| | ]
[MCell 6 |130|NOD data_p8_6_0| |*]
[MCell 7 |132| -| | ]
4 [IOpin 4 | 37| IO data_4_|*|*]
[RegIn 4 |134| -| | ]
[MCell 8 |133| IO data_3_| | ]
[MCell 9 |135| IO data_4_| | ]
5 [IOpin 5 | 38| IO data_5_|*|*]
[RegIn 5 |137| -| | ]
[MCell 10 |136| -| | ]
[MCell 11 |138| -| | ]
6 [IOpin 6 | 39| IO data_6_|*|*]
[RegIn 6 |140| -| | ]
[MCell 12 |139| IO data_5_| | ]
[MCell 13 |141|NOD N_106_iZ0| |*]
7 [IOpin 7 | 40| IO data_7_|*|*]
[RegIn 7 |143| -| | ]
[MCell 14 |142| -| | ]
[MCell 15 |144| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Logic Array Fan-in
===========================================================================
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| Mcel 2 9 ( 111)| data_p7_3
Mux01| Mcel 1 6 ( 82)| un1_un1_data_p821
Mux02| IOPin 2 0 ( 27)| adresse_5_
Mux03| IOPin 2 2 ( 25)| adresse_3_
Mux04| IOPin 2 6 ( 21)| wr
Mux05| Mcel 1 13 ( 93)| data_p2_2
Mux06| Input Pin ( 29)| reset
Mux07| Mcel 0 10 ( 64)| data_p2_7
Mux08| IOPin 2 4 ( 23)| adresse_1_
Mux09| IOPin 2 1 ( 26)| adresse_4_
Mux10| Mcel 2 0 ( 97)| data_p2_6
Mux11| ... | ...
Mux12| Mcel 2 1 ( 99)| data_p2_1
Mux13| ... | ...
Mux14| ... | ...
Mux15| Mcel 2 2 ( 100)| data_p7_1
Mux16| IOPin 1 7 ( 16)| cs
Mux17| IOPin 2 5 ( 22)| adresse_0_
Mux18| Mcel 2 6 ( 106)| data_p7_0
Mux19| Mcel 2 13 ( 117)| data_p7_2
Mux20| Mcel 2 5 ( 105)| data_p2_0
Mux21| IOPin 2 3 ( 24)| adresse_2_
Mux22| ... | ...
Mux23| Mcel 0 2 ( 52)| data_p8_6
Mux24| Mcel 2 8 ( 109)| data_p2_4
Mux25| Mcel 2 4 ( 103)| data_p2_5
Mux26| Mcel 1 9 ( 87)| Port_sel_un109_data_iZ0
Mux27| Mcel 2 12 ( 115)| data_p2_3
Mux28| IOPin 2 7 ( 20)| rd
Mux29| ... | ...
Mux30| ... | ...
Mux31| Mcel 0 13 ( 69)| data_p8_7
Mux32| ... | ...
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