output_pld.exf

TQ公司的STK16x开发系统的源码

Section Type   Array Num   Name                     Real Name          Base     Number     Increment
// -------------------------------------------------------------------------------------------------
      Port          1      adresse(5:0)                  adresse                  5          6            -1
      Port          2      p2(7:0)                       p2                  7          8            -1
      Port          3      p7(3:0)                       p7                  3          4            -1
      Port          4      p8(7:6)                       p8                  7          2            -1
      Port          5      data(7:0)                     data                  7          8            -1
End
Section Member   Rename                   Array-Notation          Array Number     Index
// -------------------------------------------------------------------------------------
        Port      adresse_5_                  adresse[5]                       1            0            
        Port      adresse_4_                  adresse[4]                       1            1            
        Port      adresse_3_                  adresse[3]                       1            2            
        Port      adresse_2_                  adresse[2]                       1            3            
        Port      adresse_1_                  adresse[1]                       1            4            
        Port      adresse_0_                  adresse[0]                       1            5            
        Port      data_7_                     data[7]                       5            0            
        Port      data_6_                     data[6]                       5            1            
        Port      data_5_                     data[5]                       5            2            
        Port      data_4_                     data[4]                       5            3            
        Port      data_3_                     data[3]                       5            4            
        Port      data_2_                     data[2]                       5            5            
        Port      data_1_                     data[1]                       5            6            
        Port      data_0_                     data[0]                       5            7            
        Port      p2_7_                       p2[7]                       2            0            
        Port      p2_6_                       p2[6]                       2            1            
        Port      p2_5_                       p2[5]                       2            2            
        Port      p2_4_                       p2[4]                       2            3            
        Port      p2_3_                       p2[3]                       2            4            
        Port      p2_2_                       p2[2]                       2            5            
        Port      p2_1_                       p2[1]                       2            6            
        Port      p2_0_                       p2[0]                       2            7            
        Port      p7_3_                       p7[3]                       3            0            
        Port      p7_2_                       p7[2]                       3            1            
        Port      p7_1_                       p7[1]                       3            2            
        Port      p7_0_                       p7[0]                       3            3            
        Port      p8_7_                       p8[7]                       4            0            
        Port      p8_6_                       p8[6]                       4            1            
End
Section Cross Reference File
Design 'OUTPUT_PLD' created Wed May 28 08:15:11 2003
   Type              New Name                               Original Name
// ----------------------------------------------------------------------
End
Section Type      Name
// ----------------------------------------------------------------------
        Input     adresse_5_
        Input     reset
        Input     rd
        Input     wr
        Input     cs
        Input     adresse_4_
        Input     adresse_3_
        Input     adresse_2_
        Input     adresse_1_
        Input     adresse_0_
        Output     p2_7_
        Output     p7_3_
        Output     p8_7_
        Output     p2_6_
        Output     p2_5_
        Output     p2_4_
        Output     p2_3_
        Output     p2_2_
        Output     p2_1_
        Output     p2_0_
        Output     p7_2_
        Output     p7_1_
        Output     p7_0_
        Output     p8_6_
        Bidi     data_7_
        Bidi     data_6_
        Bidi     data_5_
        Bidi     data_4_
        Bidi     data_3_
        Bidi     data_2_
        Bidi     data_1_
        Bidi     data_0_
End