test_pld.vhd

TQ公司的STK16x开发系统的源码

library ieee;
use ieee.std_logic_1164.all;

entity Test_PLD is
	PORT	(
		 adresse:	IN	std_logic_vector (5 downto 0);
--		 clk	:	IN	std_logic;
--		 reset	:	IN	std_logic;
		 rd     :	IN	std_logic;
		 wr 	:	IN	std_logic;
		 cs  	:	IN	std_logic;
		 data   :	INOUT 	std_logic_vector(7 downto 0);
		 p2     :	INOUT	std_logic_vector(7 downto 0);
		 p7	:	INOUT	std_logic_vector(3 downto 0); 
		 p8_6	:	INOUT	std_logic;
		 p8_7	:	INOUT	std_logic);
--		 p9_5	:	INOUT	std_logic);
end Test_PLD; 

architecture ein_einfacher_Test of Test_PLD is

--	constant	selP2: std_logic_vector (7 downto 0) := X"08";
--	constant	selP7: std_logic_vector (7 downto 0) := X"09";
--	constant	selP8: std_logic_vector (7 downto 0) := X"0A";

begin
sel_rd: process (cs, rd, wr, adresse, p2, p7, p8_7, p8_6) -- clk und reset in die sensitivity list! 	
begin

--if reset ='0' then
--  data <= (others => '0');
--elsif clk = '1' and clk'event then

case wr&cs&rd&adresse is
when "100001000" =>  data <= p2;
when "100001001" =>  data(0) <= p7(0);
                    data(1) <= p7(1);
                    data(2) <= p7(2);
                    data(3) <= p7(3);
                    data(4) <= '0'; 
                    data(5) <= '0'; 
                    data(6) <= '0'; 
               	    data(7) <= '0'; 
when "100001010" =>  data(1) <= '0';              
                    data(2) <= '0'; 
                    data(3) <= '0'; 
                    data(4) <= '0'; 
                    data(5) <= '0'; 
                    data(6) <= p8_6;
                    data(7) <= p8_7;
                	
when "001001000" =>  p2 <= data;
when "001001001" => p7(0) <= data(0);
                    p7(1) <= data(1);
                    p7(2) <= data(2);
                    p7(3) <= data(3);

when "001001010" => p8_6  <= data(6);
            	    p8_7  <= data(7);	
when others => data <= "ZZZZZZZZ";
end case;
--end if;
end process;	

end ein_einfacher_Test;