output.tal

TQ公司的STK16x开发系统的源码

Design Name = output.tt4
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*******************
* TIMING ANALYSIS *
*******************

Timing Analysis KEY:
One unit of delay time is equivalent to one pass 
     through the Central Switch Matrix.
..   Delay ( in this column ) not applicable to the indicated signal.
TSU, Set-Up Time ( 0 for input-paired signals ),
     represents the number of switch matrix passes between
     an input pin and a register setup before clock.
     TSU is reported on the register.
TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
     represents the number of switch matrix passes between
     a clocked register and an output pin.
     TCO is reported on the register.
TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
     represents the number of switch matrix passes between
     an input pin and an output pin.
     TPD is reported on the output pin.
TCR, Clocked Output-to-Register Time,
     represents the number of switch matrix passes between
     a clocked register and the register it drives ( before clock ).
     TCR is reported on the driving register.

                    TSU       TCO       TPD       TCR
                  #passes   #passes   #passes   #passes
SIGNAL NAME       min  max  min  max  min  max  min  max
           p2_7_  ..   ..   ..   ..    1    1   ..   ..   
           p7_3_  ..   ..   ..   ..    1    1   ..   ..   
           p8_7_  ..   ..   ..   ..    1    1   ..   ..   
           p2_6_  ..   ..   ..   ..    1    1   ..   ..   
           p2_5_  ..   ..   ..   ..    1    1   ..   ..   
           p2_4_  ..   ..   ..   ..    1    1   ..   ..   
           p2_3_  ..   ..   ..   ..    1    1   ..   ..   
           p2_2_  ..   ..   ..   ..    1    1   ..   ..   
           p2_1_  ..   ..   ..   ..    1    1   ..   ..   
           p2_0_  ..   ..   ..   ..    1    1   ..   ..   
           p7_2_  ..   ..   ..   ..    1    1   ..   ..   
           p7_1_  ..   ..   ..   ..    1    1   ..   ..   
           p7_0_  ..   ..   ..   ..    1    1   ..   ..   
           p8_6_  ..   ..   ..   ..    1    1   ..   ..   
         data_7_   1    1    0    0   ..   ..   ..   ..   
         data_6_   1    1    0    0   ..   ..   ..   ..   
         data_5_   1    1    0    0   ..   ..   ..   ..   
         data_4_   1    1    0    0   ..   ..   ..   ..   
         data_3_   1    1    0    0   ..   ..   ..   ..   
         data_2_   1    1    0    0   ..   ..   ..   ..   
         data_1_   1    1    0    0   ..   ..   ..   ..   
         data_0_   1    1    0    0   ..   ..   ..   ..   
un1_un1_data_p821   1    1   ..   ..   ..   ..   ..   ..   
       data_p7_0   1    1    1    1   ..   ..    1    1   
       data_p7_1   1    1    1    1   ..   ..    1    1   
       data_p7_2   1    1    1    1   ..   ..    1    1   
       data_p7_3   1    1    1    1   ..   ..    1    1   
       data_p2_0   1    1    1    1   ..   ..    1    1   
       data_p2_1   1    1    1    1   ..   ..    1    1   
       data_p2_2   1    1    1    1   ..   ..    1    1   
       data_p2_3   1    1    1    1   ..   ..    1    1   
       data_p2_4   1    1    1    1   ..   ..    1    1   
       data_p2_5   1    1    1    1   ..   ..    1    1   
       data_p2_6   1    1    1    1   ..   ..    1    1   
       data_p2_7   1    1    1    1   ..   ..    1    1   
       data_p8_6   1    1    1    1   ..   ..    1    1   
       data_p8_7   1    1    1    1   ..   ..    1    1   
       N_106_iZ0  ..   ..   ..   ..    1    1   ..   ..   
       N_108_iZ0  ..   ..   ..   ..    1    1   ..   ..   
Port_sel_un109_data_iZ0  ..   ..   ..   ..    1    1   ..   ..   
     data_p8_6_0  ..   ..   ..   ..    1    1   ..   ..