output.trp

TQ公司的STK16x开发系统的源码

Timing Report for STAMP

//  Project = output
//  Family  = mach4a
//  Device  = mach468a
//  Speed   = -5.5
//  Voltage = 5.0
//  Operating Condition = COM
//  Data sheet version  = RevD-8/2000

//  Pass Bidirection = OFF
//  Pass S/R = OFF
//  Pass Latch = OFF
//  T_SU Endpoints D/T inputs = ON
//  T_SU Endpoints CE inputs = OFF
//  T_SU Endpoints S/R inputs = OFF
//  T_SU Endpoints RAM gated = ON
//  Fmax of CE = ON
//  Fmax of RAM = ON

//  Location(From => To)
//    Pin number: numeric number preceded by "p", BGA number as is
//    Macrocell number: Segment#,GLB#,Macrocell#
//                      Segment#: starts from 0 (if applicable)
//                      GLB#: starts from A..Z, AA..ZZ
//                      Macrocell#: starts from 0 to 31


Section IO
  //DESTINATION NODES;
  data[0] [bidi]
  data[1] [bidi]
  data[2] [bidi]
  data[3] [bidi]
  data[4] [bidi]
  data[5] [bidi]
  data[6] [bidi]
  data[7] [bidi]
  p2[0] [out]
  p2[1] [out]
  p2[2] [out]
  p2[3] [out]
  p2[4] [out]
  p2[5] [out]
  p2[6] [out]
  p2[7] [out]
  p7[0] [out]
  p7[1] [out]
  p7[2] [out]
  p7[3] [out]
  p8[6] [out]
  p8[7] [out]
  data_0_.LH [reg]
  data_1_.LH [reg]
  data_2_.LH [reg]
  data_3_.LH [reg]
  data_4_.LH [reg]
  data_5_.LH [reg]
  data_6_.LH [reg]
  data_7_.LH [reg]
  data_p2_0.LH [reg]
  data_p2_1.LH [reg]
  data_p2_2.LH [reg]
  data_p2_3.LH [reg]
  data_p2_4.LH [reg]
  data_p2_5.LH [reg]
  data_p2_6.LH [reg]
  data_p2_7.LH [reg]
  data_p7_0.LH [reg]
  data_p7_1.LH [reg]
  data_p7_2.LH [reg]
  data_p7_3.LH [reg]
  data_p8_6.LH [reg]
  data_p8_7.LH [reg]
  un1_un1_data_p821.LH [reg]
  data_0_.D [reg]
  data_1_.D [reg]
  data_2_.D [reg]
  data_3_.D [reg]
  data_4_.D [reg]
  data_5_.D [reg]
  data_6_.D [reg]
  data_7_.D [reg]
  data_p2_0.D [reg]
  data_p2_1.D [reg]
  data_p2_2.D [reg]
  data_p2_3.D [reg]
  data_p2_4.D [reg]
  data_p2_5.D [reg]
  data_p2_6.D [reg]
  data_p2_7.D [reg]
  data_p7_0.D [reg]
  data_p7_1.D [reg]
  data_p7_2.D [reg]
  data_p7_3.D [reg]
  data_p8_6.D [reg]
  data_p8_7.D [reg]
  un1_un1_data_p821.D [reg]

  //SOURCE NODES;
  adresse[0] [in]
  adresse[1] [in]
  adresse[2] [in]
  adresse[3] [in]
  adresse[4] [in]
  adresse[5] [in]
  cs [in]
  rd [in]
  reset [in]
  wr [in]
  data[0].Q [reg]
  data[1].Q [reg]
  data[2].Q [reg]
  data[3].Q [reg]
  data[4].Q [reg]
  data[5].Q [reg]
  data[6].Q [reg]
  data[7].Q [reg]
  data_p2_0.Q [reg]
  data_p2_1.Q [reg]
  data_p2_2.Q [reg]
  data_p2_3.Q [reg]
  data_p2_4.Q [reg]
  data_p2_5.Q [reg]
  data_p2_6.Q [reg]
  data_p2_7.Q [reg]
  data_p7_0.Q [reg]
  data_p7_1.Q [reg]
  data_p7_2.Q [reg]
  data_p7_3.Q [reg]
  data_p8_6.Q [reg]
  data_p8_7.Q [reg]
  un1_un1_data_p821.Q [reg]


Section fMAX

  Maximum Operating Frequency: 111.11 MHz
  Clock Source From:           adresse[5]
  Logic Levels:                1
  Path Delay:                  9.0 ns
  Path Expansion                                Source                        Destination
  ==============                                ======                        ===========