test_pld_1.srr

TQ公司的STK16x开发系统的源码

$ Start of Compile
#Tue May 27 11:01:01 2003

Synplicity VHDL Compiler, version 7.1, Build 158R, built Apr 18 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!
File H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd changed - recompiling
Synthesizing work.test_pld.ein_einfacher_test
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":29:10:29:16|Incomplete sensitivity list - assuming completeness
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":89:36:89:41|Referenced variable dir_p2 is not in sensitivity list
Post processing for work.test_pld.ein_einfacher_test
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of dir_p2, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal dir_p2(7 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of NoName, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal NoName, probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal data(0), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal data(1), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal data(2), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal data(3), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal data(4), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal data(5), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal data(6), probably caused by a missing assignment in an if or case stmt
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Too many clocks (> 8) for set/reset analysis of data, try moving enabling expressions outside process
@W:"H:\TMP\Lattice\TQS_1\TQS\test_pld_1.vhd":33:0:33:1|Latch generated from process for signal data(7), probably caused by a missing assignment in an if or case stmt
@END
Process took 0.14 seconds realtime, 0.14 seconds cputime
Synplicity CPLD Technology Mapper, version 7.1, Build 144R, built Mar 28 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved
---------------------------------------
Resource Usage Report

Simple gate primitives:
IBUF            23 uses
BI_DIR          8 uses
INV             68 uses
AND2            114 uses
DLAT            17 uses


Writing encrypted edif
Mapper successful!
Process took 0.329 seconds realtime, 0.328 seconds cputime