output.vhd

TQ公司的STK16x开发系统的源码

library ieee;
use ieee.std_logic_1164.all;

entity Output_PLD is
	PORT	(
		 adresse:	IN	std_logic_vector (5 downto 0);
---		 clk	:	IN	std_logic;
		 reset	:	IN	std_logic;
		 rd     :	IN	std_logic;
		 wr 	:	IN	std_logic;
		 cs  	:	IN	std_logic;
		 data   :	INOUT 	std_logic_vector(7 downto 0);
		 p2     :	INOUT	std_logic_vector(7 downto 0);
		 p7	:	INOUT	std_logic_vector(3 downto 0); 
		 p8	:	INOUT	std_logic_vector(7 downto 6) 
		 );
--		 p9_5	:	INOUT	std_logic);
end Output_PLD; 

architecture Output of Output_PLD is 

      signal data_p2: std_logic_vector (7 downto 0);
      signal data_p7: std_logic_vector (3 downto 0);
      signal data_p8: std_logic_vector (7 downto 6);
begin



Port_sel: process (wr, rd, cs, adresse, p2, p7, p8) -- clk in die sensitivity list! 	

begin

    if reset = '0' then 
	data <= "ZZZZZZZZ";
	p2 <= "00000000";
        p7 <= "0000";
        p8 <= "00";
        data_p2 <= "00000000";
        data_p7 <= "0000";
        data_p8 <= "00";
    else 

      case wr&rd&cs&adresse is
        when "010001000" => data_p2 <= data;
        when "010001001" => data_p7(0) <= data(0);
                            data_p7(1) <= data(1);
                            data_p7(2) <= data(2);
                            data_p7(3) <= data(3);
        when "010001010" => data_p8(6) <= data(6);
                            data_p8(7) <= data(7);
        when "100001000" => data <= data_p2;
        when "100001001" => data(0) <= data_p7(0);
                            data(1) <= data_p7(1);
                            data(2) <= data_p7(2);
                            data(3) <= data_p7(3);
                            data(4) <= '0';
                            data(5) <= '0'; 
                            data(6) <= '0';
                            data(7) <= '0';  
	when "100001010" => data(6) <= data_p8(6);
                            data(7) <= data_p8(7);
                            data(0) <= '0';
                            data(1) <= '0'; 
                            data(2) <= '0';
                            data(3) <= '0';
                            data(4) <= '0';
                            data(5) <= '0'; 
        when others =>      data <= "ZZZZZZZZ";
      end case;
     
      p2 <= data_p2;
      p7 <= data_p7; 
      p8 <= data_p8;
  
    end if; 
  end process;	


end Output;