output.vcl

TQ公司的STK16x开发系统的源码

[DEVICE]

Family = M4A5;
PartType = M4A5-64/32;
Package = 48TQFP;
PartNumber = M4A5-64/32-55VC48;
Speed = -5.5;
Operating_condition = COM;
EN_Segment = NO;
Pin_MC_1to1 = NO;
Voltage = 5.0;

[REVISION]

RCS = "$Revision: 1.5 $";
Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = output.tt4;
Rev = 0.01;
DATE = 5/28/03;
TIME = 08:15:12;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Schematic_VHDL;

[IGNORE ASSIGNMENTS]

Pin_Assignments = NO;
Pin_Keep_Block = NO;
Pin_Keep_Segment = NO;
Group_Assignments = NO;
Macrocell_Assignments = NO;
Macrocell_Keep_Block = NO;
Macrocell_Keep_Segment = NO;
Pin_Reservation = NO;
Timing_Constraints = NO;
Block_Reservation = NO;
Segment_Reservation = NO;
Ignore_Source_Location = NO;
Ignore_Source_Optimization = NO;
Ignore_Source_Timing = NO;

[CLEAR ASSIGNMENTS]

Pin_Assignments = NO;
Pin_Keep_Block = NO;
Pin_Keep_Segment = NO;
Group_Assignments = NO;
Macrocell_Assignments = NO;
Macrocell_Keep_Block = NO;
Macrocell_Keep_Segment = NO;
Pin_Reservation = NO;
Timing_Constraints = NO;
Block_Reservation = NO;
Segment_Reservation = NO;
Ignore_Source_Location = NO;
Ignore_Source_Optimization = NO;
Ignore_Source_Timing = NO;

[BACKANNOTATE NETLIST]

Netlist = VHDL;
Delay_File = SDF;
Generic_VCC = ;
Generic_GND = ;

[BACKANNOTATE ASSIGNMENTS]

Pin_Assignment = NO;
Pin_Block = NO;
Pin_Macrocell_Block = NO;
Routing = NO;

[GLOBAL PROJECT OPTIMIZATION]

Balanced_Partitioning = YES;
Spread_Placement = YES;
Max_Pin_Percent = 100;
Max_Macrocell_Percent = 100;
Max_Inter_Seg_Percent = 100;
Max_Seg_In_Percent = 100;
Max_Blk_In_Percent = 100;

[FITTER REPORT FORMAT]

Fitter_Options = YES;
Pinout_Diagram = NO;
Pinout_Listing = YES;
Detailed_Block_Segment_Summary = YES;
Input_Signal_List = YES;
Output_Signal_List = YES;
Bidir_Signal_List = YES;
Node_Signal_List = YES;
Signal_Fanout_List = YES;
Block_Segment_Fanin_List = YES;
Prefit_Eqn = YES;
Postfit_Eqn = YES;
Page_Break = YES;

[OPTIMIZATION OPTIONS]

Logic_Reduction = YES;
Max_PTerm_Split = 16;
Max_PTerm_Collapse = 16;
XOR_Synthesis = YES;
Node_Collapse = Yes;
DT_Synthesis = Yes;

[FITTER GLOBAL OPTIONS]

Run_Time = 0;
Set_Reset_Dont_Care = NO;
In_Reg_Optimize = YES;
Clock_Optimize = NO;
Conf_Unused_IOs = OUT_LOW;

[POWER]
Powerlevel = Low, High;
Default = High;
Type = GLB;

[HARDWARE DEVICE OPTIONS]
Zero_Hold_Time = No;
Signature_Word = 0;
Pull_up = No;
Out_Slew_Rate = FAST, SLOW, 0;
Device_max_fanin = 33;
Device_max_pterms = 20;
Usercode_Format = Hex;

[PIN RESERVATIONS]
layer = OFF;

[LOCATION ASSIGNMENT]

Layer = OFF
data_6_ = OUTPUT,39,3,-;
data_2_ = OUTPUT,35,3,-;
data_7_ = OUTPUT,40,3,-;
data_3_ = OUTPUT,36,3,-;
data_1_ = OUTPUT,34,3,-;
data_0_ = OUTPUT,33,3,-;
data_5_ = OUTPUT,38,3,-;
data_4_ = OUTPUT,37,3,-;
p2_4_ = OUTPUT,48,0,-;
p2_3_ = OUTPUT,47,0,-;
p2_2_ = OUTPUT,46,0,-;
p2_1_ = OUTPUT,45,0,-;
p2_0_ = OUTPUT,44,0,-;
p8_7_ = OUTPUT,14,1,-;
p8_6_ = OUTPUT,13,1,-;
p7_3_ = OUTPUT,12,1,-;
p7_2_ = OUTPUT,11,1,-;
p7_1_ = OUTPUT,10,1,-;
p7_0_ = OUTPUT,9,1,-;
p2_7_ = OUTPUT,3,0,-;
p2_6_ = OUTPUT,2,0,-;
p2_5_ = OUTPUT,1,0,-;
N_106_iZ0 = NODE,*,3,-;
Port_sel_un109_data_iZ0 = NODE,*,1,-;
data_p8_7 = NODE,*,0,-;
data_p8_6 = NODE,*,0,-;
data_p2_7 = NODE,*,0,-;
data_p2_6 = NODE,*,2,-;
data_p2_5 = NODE,*,2,-;
data_p2_4 = NODE,*,2,-;
data_p2_3 = NODE,*,2,-;
data_p2_2 = NODE,*,1,-;
data_p2_1 = NODE,*,2,-;
data_p2_0 = NODE,*,2,-;
data_p7_3 = NODE,*,2,-;
data_p7_2 = NODE,*,2,-;
data_p7_1 = NODE,*,2,-;
data_p7_0 = NODE,*,2,-;
data_p8_6_0 = NODE,*,3,-;
N_108_iZ0 = NODE,*,1,-;
un1_un1_data_p821 = NODE,*,1,-;