test_pld_impl.psi

TQ公司的STK16x开发系统的源码

#
#
# Precision RTL Synthesis 2003a.1 (Release Candidate) Wed Mar 19 01:02:49 PST 2003
# 
# Copyright (c) Mentor Graphics Corporation, 1996-2003, All Rights Reserved.
#                      UNPUBLISHED, LICENSED SOFTWARE.
#           CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
#         PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# 
# Running on Windows 2000 SiemersJ@NBSIEMERSJ Service Pack 2 5.00.2195 i1586
# 
#                                  NOTICE
#
# This source code belongs to Mentor Graphics Corporation.  It is considered
# trade secret and is not to be divulged or used by parties who have not
# received written authorization from the owner.
#
#
# Date : Mon May 19 10:35:31 2003
# Designer : SiemersJ
#
#


## Working Directory
set_working_dir C:/TQS


## Technology Settings
setup_design -manufacturer Lattice -family {MACH 4A} -part M4A3-32/32-5JC


## Input File Settings
add_input_file -format VHDL -work work -compile_time 1053333380 test_pld.vhd


## Output File Settings
setup_design -basename=Test_PLD


## Design Settings
setup_design -addio
setup_design -vhdl=false
setup_design -verilog=false
setup_design -edif
setup_design -vendor_constraint_file
setup_design -transformations
setup_design -retiming=false
setup_design -advanced_fsm_optimization
setup_design -use_safe_fsm=false
setup_design -encoding=auto
setup_design -resource_sharing
setup_design -fault_tolerant=false
setup_design -frequency=
setup_design -radhardmethod=
setup_design -input_delay=0
setup_design -output_delay=0
setup_design -search_path=


## Place and Route Settings for Flow 'ispLEVER' Command 'Integrated Place and Route'
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -install_dir {C:\ispTOOLS_30\ispFPGA/..}
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -no_exec 0
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -opt_for {}
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -ba_format VHDL
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -max_pterm_split {}
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -max_pterm_collapse {}
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -max_pterm_limit {}
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -max_fanin {}
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -max_symbols {}
setup_place_and_route -flow ispLEVER -command {Integrated Place and Route} -fmax_logic_levels {}


## Place and Route Settings for Flow 'ispLEVER' Command 'Launch ispLEVER'
setup_place_and_route -flow ispLEVER -command {Launch ispLEVER} -install_dir {C:\ispTOOLS_30\ispFPGA/..}
setup_place_and_route -flow ispLEVER -command {Launch ispLEVER} -no_exec 0


## Place and Route Settings for Flow 'ispLEVER' Command 'Launch ispExplorer'
setup_place_and_route -flow ispLEVER -command {Launch ispExplorer} -install_dir {C:\ispTOOLS_30\ispFPGA/..}
setup_place_and_route -flow ispLEVER -command {Launch ispExplorer} -no_exec 0


## Design flow and state information
go -set_flow rtl -set_state compile