📄 input_pld.vhm
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II_RD: IBUF port map (
O => RD_C,
I0 => rd);
II_WR: IBUF port map (
O => WR_C,
I0 => wr);
II_CS: IBUF port map (
O => CS_C,
I0 => cs);
\II_DATA[0]\: BUFTH port map (
O => data(0),
I0 => DATA_1(0),
OE => UN1_UN19_WR);
\II_DATA[1]\: BUFTH port map (
O => data(1),
I0 => DATA_1(1),
OE => UN1_UN19_WR);
\II_DATA[2]\: BUFTH port map (
O => data(2),
I0 => DATA_1(2),
OE => UN1_UN19_WR);
\II_DATA[3]\: BUFTH port map (
O => data(3),
I0 => DATA_1(3),
OE => UN1_UN19_WR);
\II_DATA[4]\: BUFTH port map (
O => data(4),
I0 => DATA_1(4),
OE => UN1_UN19_WR);
\II_DATA[5]\: BUFTH port map (
O => data(5),
I0 => DATA_1(5),
OE => UN1_UN19_WR);
\II_DATA[6]\: BUFTH port map (
O => data(6),
I0 => DATA_1(6),
OE => UN1_UN19_WR);
\II_DATA[7]\: BUFTH port map (
O => data(7),
I0 => DATA_1(7),
OE => UN1_UN19_WR);
\II_P2[0]\: BI_DIR port map (
O => P2_C(0),
I0 => GND,
IO => p2(0),
OE => GND);
\II_P2[1]\: BI_DIR port map (
O => P2_C(1),
I0 => GND,
IO => p2(1),
OE => GND);
\II_P2[2]\: BI_DIR port map (
O => P2_C(2),
I0 => GND,
IO => p2(2),
OE => GND);
\II_P2[3]\: BI_DIR port map (
O => P2_C(3),
I0 => GND,
IO => p2(3),
OE => GND);
\II_P2[4]\: BI_DIR port map (
O => P2_C(4),
I0 => GND,
IO => p2(4),
OE => GND);
\II_P2[5]\: BI_DIR port map (
O => P2_C(5),
I0 => GND,
IO => p2(5),
OE => GND);
\II_P2[6]\: BI_DIR port map (
O => P2_C(6),
I0 => GND,
IO => p2(6),
OE => GND);
\II_P2[7]\: BI_DIR port map (
O => P2_C(7),
I0 => GND,
IO => p2(7),
OE => GND);
\II_P7[0]\: BI_DIR port map (
O => P7_C(0),
I0 => GND,
IO => p7(0),
OE => GND);
\II_P7[1]\: BI_DIR port map (
O => P7_C(1),
I0 => GND,
IO => p7(1),
OE => GND);
\II_P7[2]\: BI_DIR port map (
O => P7_C(2),
I0 => GND,
IO => p7(2),
OE => GND);
\II_P7[3]\: BI_DIR port map (
O => P7_C(3),
I0 => GND,
IO => p7(3),
OE => GND);
\II_P8[6]\: BI_DIR port map (
O => P8_C(6),
I0 => GND,
IO => p8(6),
OE => GND);
\II_P8[7]\: BI_DIR port map (
O => P8_C(7),
I0 => GND,
IO => p8(7),
OE => GND);
\II_ADRESSE_C_I[0]\: INV port map (
O => ADRESSE_C_I(0),
I0 => ADRESSE_C(0));
\II_ADRESSE_C_I[1]\: INV port map (
O => ADRESSE_C_I(1),
I0 => ADRESSE_C(1));
II_N_51_I: INV port map (
O => N_51_I,
I0 => N_51);
II_N_50_I: INV port map (
O => N_50_I,
I0 => N_50);
II_G_19: AND2 port map (
O => N_46,
I0 => N_57,
I1 => N_59);
\II_UN1_P2_0_AND2[5]\: AND2 port map (
O => N_29,
I0 => N_46,
I1 => N_61);
\II_UN1_P2_0_AND2[4]\: AND2 port map (
O => N_28,
I0 => N_46,
I1 => N_60);
II_G_19_38: AND2 port map (
O => N_57,
I0 => ADRESSE_C(3),
I1 => ADRESSE_C_I(4));
II_G_19_39: AND2 port map (
O => N_58,
I0 => ADRESSE_C_I(2),
I1 => CS_C_I);
II_G_19_40: AND2 port map (
O => N_59,
I0 => ADRESSE_C_I(5),
I1 => N_58);
II_UN1_P2_0_AND2_4_41: AND2 port map (
O => N_60,
I0 => P2_C(4),
I1 => N_41);
II_UN1_P2_0_AND2_5_42: AND2 port map (
O => N_61,
I0 => P2_C(5),
I1 => N_41);
\II_ADRESSE_C_I[5]\: INV port map (
O => ADRESSE_C_I(5),
I0 => ADRESSE_C(5));
\II_ADRESSE_C_I[2]\: INV port map (
O => ADRESSE_C_I(2),
I0 => ADRESSE_C(2));
II_CS_C_I: INV port map (
O => CS_C_I,
I0 => CS_C);
\II_ADRESSE_C_I[4]\: INV port map (
O => ADRESSE_C_I(4),
I0 => ADRESSE_C(4));
II_WR_C_I: INV port map (
O => WR_C_I,
I0 => WR_C);
II_RD_C_I: INV port map (
O => RD_C_I,
I0 => RD_C);
II_N_45_I: INV port map (
O => N_45_I,
I0 => N_45);
\II_UN1_P2_1_0_3_.R\: INV port map (
O => \UN1_P2_1_0_3_.UN3\,
I0 => ADRESSE_C(0));
\II_UN1_P2_1_0_3_.M\: AND2 port map (
O => \UN1_P2_1_0_3_.UN1\,
I0 => P7_C(3),
I1 => ADRESSE_C(0));
\II_UN1_P2_1_0_3_.N\: AND2 port map (
O => \UN1_P2_1_0_3_.UN0\,
I0 => P2_C(3),
I1 => \UN1_P2_1_0_3_.UN3\);
\II_UN1_P2_1_0_3_.P\: OR2 port map (
O => N_11,
I0 => \UN1_P2_1_0_3_.UN1\,
I1 => \UN1_P2_1_0_3_.UN0\);
II_G_20: AND2 port map (
O => N_41,
I0 => ADRESSE_C_I(0),
I1 => ADRESSE_C_I(1));
II_G_21: AND2 port map (
O => N_51,
I0 => ADRESSE_C(0),
I1 => ADRESSE_C(1));
\II_SEL_RD.UN19_WR_0_AND2\: AND2 port map (
O => \SEL_RD.UN19_WR\,
I0 => N_46,
I1 => N_51_I);
\II_UN1_P2_2_0_0_AND2[0]\: AND2 port map (
O => N_31,
I0 => N_5,
I1 => ADRESSE_C_I(1));
\II_UN1_P2_2_0_0_AND2[1]\: AND2 port map (
O => N_32,
I0 => N_7,
I1 => ADRESSE_C_I(1));
\II_UN1_P2_2_0_0_AND2[2]\: AND2 port map (
O => N_33,
I0 => N_9,
I1 => ADRESSE_C_I(1));
\II_UN1_P2_2_0_0_AND2[3]\: AND2 port map (
O => N_34,
I0 => N_11,
I1 => ADRESSE_C_I(1));
\II_UN1_P2_1_0_0_AND2[6]\: AND2 port map (
O => N_35,
I0 => ADRESSE_C_I(0),
I1 => P2_C(6));
\II_UN1_P2_1_0_0_AND2[7]\: AND2 port map (
O => N_36,
I0 => ADRESSE_C_I(0),
I1 => P2_C(7));
II_UN1_UN26_WR_0: AND2 port map (
O => N_50,
I0 => N_45_I,
I1 => RESET_C);
\II_SEL_RD.UN2_WR_0_AND3\: AND2 port map (
O => \SEL_RD.UN2_WR\,
I0 => RD_C_I,
I1 => WR_C);
II_UN1_UN26_WR_0_AND3: AND2 port map (
O => N_45,
I0 => RD_C,
I1 => WR_C_I);
II_UN1_UN19_WR: DLATRH port map (
Q => UN1_UN19_WR,
D => \SEL_RD.UN19_WR\,
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_DATA_1[4]\: DLATRH port map (
Q => DATA_1(4),
D => N_28,
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_DATA_1[5]\: DLATRH port map (
Q => DATA_1(5),
D => N_29,
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_DATA_1[0]\: DLATRH port map (
Q => DATA_1(0),
D => N_31,
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_DATA_1[1]\: DLATRH port map (
Q => DATA_1(1),
D => N_32,
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_DATA_1[2]\: DLATRH port map (
Q => DATA_1(2),
D => N_33,
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_DATA_1[3]\: DLATRH port map (
Q => DATA_1(3),
D => N_34,
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_DATA_1[6]\: DLATRH port map (
Q => DATA_1(6),
D => UN1_P2(6),
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_DATA_1[7]\: DLATRH port map (
Q => DATA_1(7),
D => UN1_P2(7),
LAT => \SEL_RD.UN2_WR\,
R => N_50_I);
\II_UN1_P2_2_0_6_.R\: INV port map (
O => \UN1_P2_2_0_6_.UN3\,
I0 => ADRESSE_C(1));
\II_UN1_P2_2_0_6_.M\: AND2 port map (
O => \UN1_P2_2_0_6_.UN1\,
I0 => P8_C(6),
I1 => ADRESSE_C(1));
\II_UN1_P2_2_0_6_.N\: AND2 port map (
O => \UN1_P2_2_0_6_.UN0\,
I0 => N_35,
I1 => \UN1_P2_2_0_6_.UN3\);
\II_UN1_P2_2_0_6_.P\: OR2 port map (
O => UN1_P2(6),
I0 => \UN1_P2_2_0_6_.UN1\,
I1 => \UN1_P2_2_0_6_.UN0\);
\II_UN1_P2_2_0_7_.R\: INV port map (
O => \UN1_P2_2_0_7_.UN3\,
I0 => ADRESSE_C(1));
\II_UN1_P2_2_0_7_.M\: AND2 port map (
O => \UN1_P2_2_0_7_.UN1\,
I0 => P8_C(7),
I1 => ADRESSE_C(1));
\II_UN1_P2_2_0_7_.N\: AND2 port map (
O => \UN1_P2_2_0_7_.UN0\,
I0 => N_36,
I1 => \UN1_P2_2_0_7_.UN3\);
\II_UN1_P2_2_0_7_.P\: OR2 port map (
O => UN1_P2(7),
I0 => \UN1_P2_2_0_7_.UN1\,
I1 => \UN1_P2_2_0_7_.UN0\);
\II_UN1_P2_1_0_0_.R\: INV port map (
O => \UN1_P2_1_0_0_.UN3\,
I0 => ADRESSE_C(0));
\II_UN1_P2_1_0_0_.M\: AND2 port map (
O => \UN1_P2_1_0_0_.UN1\,
I0 => P7_C(0),
I1 => ADRESSE_C(0));
\II_UN1_P2_1_0_0_.N\: AND2 port map (
O => \UN1_P2_1_0_0_.UN0\,
I0 => P2_C(0),
I1 => \UN1_P2_1_0_0_.UN3\);
\II_UN1_P2_1_0_0_.P\: OR2 port map (
O => N_5,
I0 => \UN1_P2_1_0_0_.UN1\,
I1 => \UN1_P2_1_0_0_.UN0\);
\II_UN1_P2_1_0_1_.R\: INV port map (
O => \UN1_P2_1_0_1_.UN3\,
I0 => ADRESSE_C(0));
\II_UN1_P2_1_0_1_.M\: AND2 port map (
O => \UN1_P2_1_0_1_.UN1\,
I0 => P7_C(1),
I1 => ADRESSE_C(0));
\II_UN1_P2_1_0_1_.N\: AND2 port map (
O => \UN1_P2_1_0_1_.UN0\,
I0 => P2_C(1),
I1 => \UN1_P2_1_0_1_.UN3\);
\II_UN1_P2_1_0_1_.P\: OR2 port map (
O => N_7,
I0 => \UN1_P2_1_0_1_.UN1\,
I1 => \UN1_P2_1_0_1_.UN0\);
\II_UN1_P2_1_0_2_.R\: INV port map (
O => \UN1_P2_1_0_2_.UN3\,
I0 => ADRESSE_C(0));
\II_UN1_P2_1_0_2_.M\: AND2 port map (
O => \UN1_P2_1_0_2_.UN1\,
I0 => P7_C(2),
I1 => ADRESSE_C(0));
\II_UN1_P2_1_0_2_.N\: AND2 port map (
O => \UN1_P2_1_0_2_.UN0\,
I0 => P2_C(2),
I1 => \UN1_P2_1_0_2_.UN3\);
\II_UN1_P2_1_0_2_.P\: OR2 port map (
O => N_9,
I0 => \UN1_P2_1_0_2_.UN1\,
I1 => \UN1_P2_1_0_2_.UN0\);
VCC <= '1';
end beh;
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