📄 input_pld.vhm

📁 TQ公司的STK16x开发系统的源码
💻 VHM
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--
-- Written by Synplicity
-- Wed May 28 07:10:33 2003
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity MACH_LATCH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  LAT :  in std_logic;
  R :  in std_logic;
  S :  in std_logic;
  NOTIFIER :  in std_logic);
end MACH_LATCH;

architecture beh of MACH_LATCH is
  signal UN0 : std_logic ;
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  UN0 <= not S;
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  II_Q: prim_latch port map (Q, D, LAT, UN1, UN0);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity AND2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 and I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity BI_DIR is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  IO :  inout std_logic;
  OE :  in std_logic);
end BI_DIR;

architecture beh of BI_DIR is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  IO <= I0 after 100 ps when OE = '1' else 'Z' after 100 ps;
  O <= IO;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity BUFTH is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  OE :  in std_logic);
end BUFTH;

architecture beh of BUFTH is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 after 100 ps when OE = '1' else 'Z' after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity DLATRH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  LAT :  in std_logic;
  R :  in std_logic);
end DLATRH;

architecture beh of DLATRH is
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_LATCH
    port(
      Q :  out std_logic;
      D :  in std_logic;
      LAT :  in std_logic;
      R :  in std_logic;
      S :  in std_logic;
      NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS5: MACH_LATCH port map (
      Q => Q,
      D => D,
      LAT => LAT,
      R => UN1,
      S => NN_1,
      NOTIFIER => NOTIFIER);
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity IBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity INV is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end INV;

architecture beh of INV is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= not I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OR2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end OR2;

architecture beh of OR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 or I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity Input_PLD is
port(
  adresse : in std_logic_vector(5 downto 0);
  reset :  in std_logic;
  rd :  in std_logic;
  wr :  in std_logic;
  cs :  in std_logic;
  data : out std_logic_vector(7 downto 0);
  p2 : inout std_logic_vector(7 downto 0);
  p7 : inout std_logic_vector(3 downto 0);
  p8 : inout std_logic_vector(7 downto 6));
end Input_PLD;

architecture beh of Input_PLD is
  signal DATA_1 : std_logic_vector(7 downto 0);
  signal UN1_P2 : std_logic_vector(7 downto 6);
  signal ADRESSE_C : std_logic_vector(5 downto 0);
  signal P2_C : std_logic_vector(7 downto 0);
  signal P7_C : std_logic_vector(3 downto 0);
  signal P8_C : std_logic_vector(7 downto 6);
  signal ADRESSE_C_I : std_logic_vector(5 downto 0);
  signal UN1_UN19_WR : std_logic ;
  signal GND : std_logic ;
  signal N_5 : std_logic ;
  signal N_7 : std_logic ;
  signal N_9 : std_logic ;
  signal N_11 : std_logic ;
  signal N_28 : std_logic ;
  signal N_29 : std_logic ;
  signal N_31 : std_logic ;
  signal N_32 : std_logic ;
  signal N_33 : std_logic ;
  signal N_34 : std_logic ;
  signal N_35 : std_logic ;
  signal N_36 : std_logic ;
  signal N_41 : std_logic ;
  signal \SEL_RD.UN19_WR\ : std_logic ;
  signal N_45 : std_logic ;
  signal \SEL_RD.UN2_WR\ : std_logic ;
  signal N_46 : std_logic ;
  signal RESET_C : std_logic ;
  signal RD_C : std_logic ;
  signal WR_C : std_logic ;
  signal CS_C : std_logic ;
  signal N_50 : std_logic ;
  signal N_51 : std_logic ;
  signal N_57 : std_logic ;
  signal N_58 : std_logic ;
  signal N_59 : std_logic ;
  signal N_60 : std_logic ;
  signal N_61 : std_logic ;
  signal CS_C_I : std_logic ;
  signal WR_C_I : std_logic ;
  signal RD_C_I : std_logic ;
  signal N_45_I : std_logic ;
  signal N_51_I : std_logic ;
  signal N_50_I : std_logic ;
  signal \UN1_P2_1_0_3_.UN3\ : std_logic ;
  signal \UN1_P2_1_0_3_.UN1\ : std_logic ;
  signal \UN1_P2_1_0_3_.UN0\ : std_logic ;
  signal \UN1_P2_2_0_6_.UN3\ : std_logic ;
  signal \UN1_P2_2_0_6_.UN1\ : std_logic ;
  signal \UN1_P2_2_0_6_.UN0\ : std_logic ;
  signal \UN1_P2_2_0_7_.UN3\ : std_logic ;
  signal \UN1_P2_2_0_7_.UN1\ : std_logic ;
  signal \UN1_P2_2_0_7_.UN0\ : std_logic ;
  signal \UN1_P2_1_0_0_.UN3\ : std_logic ;
  signal \UN1_P2_1_0_0_.UN1\ : std_logic ;
  signal \UN1_P2_1_0_0_.UN0\ : std_logic ;
  signal \UN1_P2_1_0_1_.UN3\ : std_logic ;
  signal \UN1_P2_1_0_1_.UN1\ : std_logic ;
  signal \UN1_P2_1_0_1_.UN0\ : std_logic ;
  signal \UN1_P2_1_0_2_.UN3\ : std_logic ;
  signal \UN1_P2_1_0_2_.UN1\ : std_logic ;
  signal \UN1_P2_1_0_2_.UN0\ : std_logic ;
  signal VCC : std_logic ;
  component IBUF
    port(
      O :  out std_logic;
      I0 :  in std_logic  );
  end component;
  component BUFTH
    port(
      O :  out std_logic;
      I0 :  in std_logic;
      OE :  in std_logic  );
  end component;
  component BI_DIR
    port(
      O :  out std_logic;
      I0 :  in std_logic;
      IO :  inout std_logic;
      OE :  in std_logic  );
  end component;
  component INV
    port(
      O :  out std_logic;
      I0 :  in std_logic  );
  end component;
  component AND2
    port(
      O :  out std_logic;
      I0 :  in std_logic;
      I1 :  in std_logic  );
  end component;
  component OR2
    port(
      O :  out std_logic;
      I0 :  in std_logic;
      I1 :  in std_logic  );
  end component;
  component DLATRH
    port(
      Q :  out std_logic;
      D :  in std_logic;
      LAT :  in std_logic;
      R :  in std_logic  );
  end component;
begin
  GND <= '0';
  \II_ADRESSE[0]\: IBUF port map (
      O => ADRESSE_C(0),
      I0 => adresse(0));
  \II_ADRESSE[1]\: IBUF port map (
      O => ADRESSE_C(1),
      I0 => adresse(1));
  \II_ADRESSE[2]\: IBUF port map (
      O => ADRESSE_C(2),
      I0 => adresse(2));
  \II_ADRESSE[3]\: IBUF port map (
      O => ADRESSE_C(3),
      I0 => adresse(3));
  \II_ADRESSE[4]\: IBUF port map (
      O => ADRESSE_C(4),
      I0 => adresse(4));
  \II_ADRESSE[5]\: IBUF port map (
      O => ADRESSE_C(5),
      I0 => adresse(5));
  II_RESET: IBUF port map (
      O => RESET_C,
      I0 => reset);
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