📄 input.prd
字号:
Mux19| ... | ...
Mux20| ... | ...
Mux21| IOPin 2 3 ( 24)| adresse_2_
Mux22| ... | ...
Mux23| ... | ...
Mux24| ... | ...
Mux25| ... | ...
Mux26| ... | ...
Mux27| ... | ...
Mux28| ... | ...
Mux29| ... | ...
Mux30| ... | ...
Mux31| ... | ...
Mux32| ... | ...
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| data_7_|OUT| | A | 2 | 2 to [ 0]| 1 XOR free
1| data_0_|OUT| | A | 2 | 2 to [ 1]| 1 XOR free
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| data_2_|OUT| | A | 2 | 2 to [ 4]| 1 XOR free
5| data_1_|OUT| | A | 2 | 2 to [ 5]| 1 XOR free
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| data_3_|OUT| | A | 2 | 2 to [ 8]| 1 XOR free
9| data_4_|OUT| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| data_6_|OUT| | A | 2 | 2 to [12]| 1 XOR free
13| data_5_|OUT| | A | 1 | 2 free | 1 XOR to [13] for 1 PT sig
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| data_7_|OUT| | A | 2 |=> can support up to [ 8] logic PT(s)
1| data_0_|OUT| | A | 2 |=> can support up to [ 13] logic PT(s)
2| | ? | | S | |=> can support up to [ 10] logic PT(s)
3| | ? | | S | |=> can support up to [ 10] logic PT(s)
4| data_2_|OUT| | A | 2 |=> can support up to [ 13] logic PT(s)
5| data_1_|OUT| | A | 2 |=> can support up to [ 13] logic PT(s)
6| | ? | | S | |=> can support up to [ 10] logic PT(s)
7| | ? | | S | |=> can support up to [ 12] logic PT(s)
8| data_3_|OUT| | A | 2 |=> can support up to [ 15] logic PT(s)
9| data_4_|OUT| | A | 1 |=> can support up to [ 13] logic PT(s)
10| | ? | | S | |=> can support up to [ 12] logic PT(s)
11| | ? | | S | |=> can support up to [ 12] logic PT(s)
12| data_6_|OUT| | A | 2 |=> can support up to [ 15] logic PT(s)
13| data_5_|OUT| | A | 1 |=> can support up to [ 13] logic PT(s)
14| | ? | | S | |=> can support up to [ 12] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 3] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| data_7_|OUT| | => | 5 6 ( 7) 0 | 38 39 ( 40) 33
1| data_0_|OUT| | => | 5 6 7 ( 0)| 38 39 40 ( 33)
2| | | | => | 6 7 0 1 | 39 40 33 34
3| | | | => | 6 7 0 1 | 39 40 33 34
4| data_2_|OUT| | => | 7 0 1 ( 2)| 40 33 34 ( 35)
5| data_1_|OUT| | => | 7 0 ( 1) 2 | 40 33 ( 34) 35
6| | | | => | 0 1 2 3 | 33 34 35 36
7| | | | => | 0 1 2 3 | 33 34 35 36
8| data_3_|OUT| | => | 1 2 ( 3) 4 | 34 35 ( 36) 37
9| data_4_|OUT| | => | 1 2 3 ( 4)| 34 35 36 ( 37)
10| | | | => | 2 3 4 5 | 35 36 37 38
11| | | | => | 2 3 4 5 | 35 36 37 38
12| data_6_|OUT| | => | 3 4 5 ( 6)| 36 37 38 ( 39)
13| data_5_|OUT| | => | 3 4 ( 5) 6 | 36 37 ( 38) 39
14| | | | => | 4 5 6 7 | 37 38 39 40
15| | | | => | 4 5 6 7 | 37 38 39 40
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > IO-to-Node Pin Mapping
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| data_0_|OUT|*| 33| => | 0 ( 1) 2 3 4 5 6 7
1| data_1_|OUT|*| 34| => | 2 3 4 ( 5) 6 7 8 9
2| data_2_|OUT|*| 35| => | ( 4) 5 6 7 8 9 10 11
3| data_3_|OUT|*| 36| => | 6 7 ( 8) 9 10 11 12 13
4| data_4_|OUT|*| 37| => | 8 ( 9) 10 11 12 13 14 15
5| data_5_|OUT|*| 38| => | 10 11 12 (13) 14 15 0 1
6| data_6_|OUT|*| 39| => | (12) 13 14 15 0 1 2 3
7| data_7_|OUT|*| 40| => | 14 15 ( 0) 1 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > IO/Node and IO/Input Macrocell Pairing Table
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| data_0_|OUT|*| 33| => | Input macrocell [ -]
1| data_1_|OUT|*| 34| => | Input macrocell [ -]
2| data_2_|OUT|*| 35| => | Input macrocell [ -]
3| data_3_|OUT|*| 36| => | Input macrocell [ -]
4| data_4_|OUT|*| 37| => | Input macrocell [ -]
5| data_5_|OUT|*| 38| => | Input macrocell [ -]
6| data_6_|OUT|*| 39| => | Input macrocell [ -]
7| data_7_|OUT|*| 40| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 33|OUT data_0_|*| ]
[RegIn 0 |122| -| | ]
[MCell 0 |121|OUT data_7_| | ]
[MCell 1 |123|OUT data_0_| | ]
1 [IOpin 1 | 34|OUT data_1_|*| ]
[RegIn 1 |125| -| | ]
[MCell 2 |124| -| | ]
[MCell 3 |126| -| | ]
2 [IOpin 2 | 35|OUT data_2_|*| ]
[RegIn 2 |128| -| | ]
[MCell 4 |127|OUT data_2_| | ]
[MCell 5 |129|OUT data_1_| | ]
3 [IOpin 3 | 36|OUT data_3_|*| ]
[RegIn 3 |131| -| | ]
[MCell 6 |130| -| | ]
[MCell 7 |132| -| | ]
4 [IOpin 4 | 37|OUT data_4_|*| ]
[RegIn 4 |134| -| | ]
[MCell 8 |133|OUT data_3_| | ]
[MCell 9 |135|OUT data_4_| | ]
5 [IOpin 5 | 38|OUT data_5_|*| ]
[RegIn 5 |137| -| | ]
[MCell 10 |136| -| | ]
[MCell 11 |138| -| | ]
6 [IOpin 6 | 39|OUT data_6_|*| ]
[RegIn 6 |140| -| | ]
[MCell 12 |139|OUT data_6_| | ]
[MCell 13 |141|OUT data_5_| | ]
7 [IOpin 7 | 40|OUT data_7_|*| ]
[RegIn 7 |143| -| | ]
[MCell 14 |142| -| | ]
[MCell 15 |144| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 3] > Logic Array Fan-in
===========================================================================
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| ... | ...
Mux01| IOPin 0 6 ( 45)| p2_1_
Mux02| IOPin 2 0 ( 27)| adresse_5_
Mux03| IOPin 1 0 ( 9)| p7_0_
Mux04| IOPin 2 6 ( 21)| wr
Mux05| IOPin 0 1 ( 2)| p2_6_
Mux06| IOPin 1 2 ( 11)| p7_2_
Mux07| ... | ...
Mux08| IOPin 0 7 ( 44)| p2_0_
Mux09| IOPin 1 5 ( 14)| p8_7_
Mux10| Mcel 2 0 ( 97)| N_50_iZ0
Mux11| IOPin 2 2 ( 25)| adresse_3_
Mux12| IOPin 2 4 ( 23)| adresse_1_
Mux13| ... | ...
Mux14| IOPin 0 4 ( 47)| p2_3_
Mux15| ... | ...
Mux16| IOPin 1 7 ( 16)| cs
Mux17| IOPin 0 0 ( 3)| p2_7_
Mux18| ... | ...
Mux19| IOPin 2 1 ( 26)| adresse_4_
Mux20| Mcel 2 4 ( 103)| un1_un19_wr
Mux21| IOPin 2 3 ( 24)| adresse_2_
Mux22| IOPin 1 4 ( 13)| p8_6_
Mux23| ... | ...
Mux24| IOPin 1 3 ( 12)| p7_3_
Mux25| IOPin 0 3 ( 48)| p2_4_
Mux26| IOPin 2 5 ( 22)| adresse_0_
Mux27| IOPin 0 2 ( 1)| p2_5_
Mux28| IOPin 2 7 ( 20)| rd
Mux29| IOPin 1 1 ( 10)| p7_1_
Mux30| IOPin 0 5 ( 46)| p2_2_
Mux31| ... | ...
Mux32| ... | ...
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